Lines Matching +full:0 +full:x1
11 u8 res0[0x10];
13 u8 res1[0x4];
20 u8 res2[0xc];
22 u8 res3[0x4];
59 u8 res4[0x28];
63 u8 res6[0xc];
66 u8 res7[0x4];
73 u8 res8[0x224];
75 u8 res9[0x14];
77 u8 res10[0x48];
84 u8 res11[0x4];
90 u8 res12[0x08];
93 u8 res13[0x200];
99 u8 res14[0x4];
101 u8 res15[0x24];
103 u8 res16[0x4];
105 u8 res17[0x34];
110 u8 res18[0x4];
112 u8 res19[0x1c];
116 u8 res20[0x14];
118 u8 res21[0x1c];
126 u8 res22[0x14];
128 u8 res23[0x8];
130 u8 res24[0x20];
133 u8 res25[0x10];
135 u8 res26[0x4];
146 u8 res27[0x18];
149 u8 res29[0x1e0];
153 u8 res30[0x10];
156 check_member(rk3288_edp, pll_reg_5, 0xa00);
159 #define VID_CAP_FUNC_EN_N (0x1 << 6)
160 #define VID_FIFO_FUNC_EN_N (0x1 << 5)
161 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
162 #define AUD_FUNC_EN_N (0x1 << 3)
163 #define HDCP_FUNC_EN_N (0x1 << 2)
164 #define SW_FUNC_EN_N (0x1 << 0)
167 #define SSC_FUNC_EN_N (0x1 << 7)
168 #define AUX_FUNC_EN_N (0x1 << 2)
169 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
170 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
173 #define VIDEO_EN (0x1 << 7)
174 #define VIDEO_MUTE (0x1 << 6)
177 #define IN_D_RANGE_MASK (0x1 << 7)
179 #define IN_D_RANGE_CEA (0x1 << 7)
180 #define IN_D_RANGE_VESA (0x0 << 7)
181 #define IN_BPC_MASK (0x7 << 4)
183 #define IN_BPC_12_BITS (0x3 << 4)
184 #define IN_BPC_10_BITS (0x2 << 4)
185 #define IN_BPC_8_BITS (0x1 << 4)
186 #define IN_BPC_6_BITS (0x0 << 4)
187 #define IN_COLOR_F_MASK (0x3 << 0)
188 #define IN_COLOR_F_SHIFT (0)
189 #define IN_COLOR_F_YCBCR444 (0x2 << 0)
190 #define IN_COLOR_F_YCBCR422 (0x1 << 0)
191 #define IN_COLOR_F_RGB (0x0 << 0)
194 #define IN_YC_COEFFI_MASK (0x1 << 7)
196 #define IN_YC_COEFFI_ITU709 (0x1 << 7)
197 #define IN_YC_COEFFI_ITU601 (0x0 << 7)
198 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
200 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
201 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
204 #define BIST_EN (0x1 << 3)
205 #define BIST_WH_64 (0x1 << 2)
206 #define BIST_WH_32 (0x0 << 2)
207 #define BIST_TYPE_COLR_BAR (0x0 << 0)
208 #define BIST_TYPE_GRAY_BAR (0x1 << 0)
209 #define BIST_TYPE_MOBILE_BAR (0x2 << 0)
212 #define VID_HRES_TH(x) (((x) & 0xf) << 4)
213 #define VID_VRES_TH(x) (((x) & 0xf) << 0)
216 #define F_SEL (0x1 << 4)
217 #define INTERACE_SCAN_CFG (0x1 << 2)
219 #define VSYNC_POLARITY_CFG (0x1 << 1)
221 #define HSYNC_POLARITY_CFG (0x1 << 0)
222 #define HSYNC_POLARITY_CFG_OFFSET 0
225 #define PD_INC_BG (0x1 << 7)
226 #define PD_EXP_BG (0x1 << 6)
227 #define PD_AUX (0x1 << 5)
228 #define PD_PLL (0x1 << 4)
229 #define PD_CH3 (0x1 << 3)
230 #define PD_CH2 (0x1 << 2)
231 #define PD_CH1 (0x1 << 1)
232 #define PD_CH0 (0x1 << 0)
235 #define REF_CLK_24M (0x1 << 1)
236 #define REF_CLK_27M (0x0 << 1)
239 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
240 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
241 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
242 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6)
243 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4)
244 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
245 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
246 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4)
247 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2)
248 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
249 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
250 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2)
251 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0)
252 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
253 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
254 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
257 #define SEL_24M (0x1 << 3)
260 #define VSYNC_DET (0x1 << 7)
261 #define PLL_LOCK_CHG (0x1 << 6)
262 #define SPDIF_ERR (0x1 << 5)
263 #define SPDIF_UNSTBL (0x1 << 4)
264 #define VID_FORMAT_CHG (0x1 << 3)
265 #define AUD_CLK_CHG (0x1 << 2)
266 #define VID_CLK_CHG (0x1 << 1)
267 #define SW_INT (0x1 << 0)
270 #define ENC_EN_CHG (0x1 << 6)
271 #define HW_BKSV_RDY (0x1 << 3)
272 #define HW_SHA_DONE (0x1 << 2)
273 #define HW_AUTH_STATE_CHG (0x1 << 1)
274 #define HW_AUTH_DONE (0x1 << 0)
277 #define AFIFO_UNDER (0x1 << 7)
278 #define AFIFO_OVER (0x1 << 6)
279 #define R0_CHK_FLAG (0x1 << 5)
282 #define PSR_ACTIVE (0x1 << 7)
283 #define PSR_INACTIVE (0x1 << 6)
284 #define SPDIF_BI_PHASE_ERR (0x1 << 5)
285 #define HOTPLUG_CHG (0x1 << 2)
286 #define HPD_LOST (0x1 << 1)
287 #define PLUG (0x1 << 0)
290 #define INT_HPD (0x1 << 6)
291 #define HW_LT_DONE (0x1 << 5)
292 #define SINK_LOST (0x1 << 3)
293 #define LINK_LOST (0x1 << 2)
294 #define RPLY_RECEIV (0x1 << 1)
295 #define AUX_ERR (0x1 << 0)
298 #define SOFT_INT_CTRL (0x1 << 2)
299 #define INT_POL (0x1 << 0)
302 #define DET_STA (0x1 << 2)
303 #define FORCE_DET (0x1 << 1)
304 #define DET_CTRL (0x1 << 0)
307 #define CHA_CRI(x) (((x) & 0xf) << 4)
308 #define CHA_STA (0x1 << 2)
309 #define FORCE_CHA (0x1 << 1)
310 #define CHA_CTRL (0x1 << 0)
313 #define HPD_STATUS (0x1 << 6)
314 #define F_HPD (0x1 << 5)
315 #define HPD_CTRL (0x1 << 4)
316 #define HDCP_RDY (0x1 << 3)
317 #define STRM_VALID (0x1 << 2)
318 #define F_VALID (0x1 << 1)
319 #define VALID_CTRL (0x1 << 0)
322 #define FIX_M_AUD (0x1 << 4)
323 #define ENHANCED (0x1 << 3)
324 #define FIX_M_VID (0x1 << 2)
325 #define M_VID_UPDATE_CTRL (0x3 << 0)
331 #define V2L_CUR_SEL_1MA (1 << 0)
335 #define LOOP_FILTER_RESET (0 << 4)
336 #define PALL_SSC_RESET (0 << 3)
337 #define LOCK_DET_BYPASS (0 << 2)
338 #define PLL_LOCK_DET_MODE (0 << 1)
339 #define PLL_LOCK_DET_FORCE (0 << 0)
343 #define STANDBY_CUR_SEL (0 << 3)
345 #define CHG_PUMP_INPUT_CTRL_OP (0 << 0)
348 #define SSC_OFFSET (0 << 6)
350 #define SSC_DEPTH (9 << 0)
354 #define PRE_DRIVER_PW_CTRL1 (0 << 5)
355 #define LP_MODE_CLK_REGULATOR (0 << 4)
356 #define RESISTOR_MSB_CTRL (0 << 3)
357 #define RESISTOR_CTRL (7 << 0)
360 #define DP_AUX_COMMON_MODE (0 << 4)
361 #define DP_AUX_EN (0 << 3)
362 #define AUX_TERM_50OHM (3 << 0)
366 #define DP_DB_CUR_CTRL (0 << 3)
368 #define DP_RESISTOR_TUNE_BG (2 << 0)
372 #define CH0_CH2_SWING_EMP_CTRL (5 << 0)
375 #define SCRAMBLING_DISABLE (0x1 << 5)
376 #define SCRAMBLING_ENABLE (0x0 << 5)
377 #define LINK_QUAL_PATTERN_SET_MASK (0x7 << 2)
378 #define LINK_QUAL_PATTERN_SET_HBR2 (0x5 << 2)
379 #define LINK_QUAL_PATTERN_SET_80BIT (0x4 << 2)
380 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
381 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
382 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
383 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
384 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
385 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
386 #define SW_TRAINING_PATTERN_SET_DISABLE (0x0 << 0)
389 #define HW_LT_ERR_CODE_MASK 0x70
391 #define HW_LT_EN (0x1 << 0)
394 #define PLL_LOCK (0x1 << 4)
395 #define F_PLL_LOCK (0x1 << 3)
396 #define PLL_LOCK_CTRL (0x1 << 2)
397 #define POLL_EN (0x1 << 1)
398 #define PN_INV (0x1 << 0)
401 #define AUX_BUSY (0x1 << 4)
402 #define AUX_STATUS_MASK (0xf << 0)
405 #define DEFER_CTRL_EN (0x1 << 7)
406 #define DEFER_COUNT(x) (((x) & 0x7f) << 0)
409 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
410 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
413 #define BUF_CLR (0x1 << 7)
414 #define BUF_HAVE_DATA (0x1 << 4)
415 #define BUF_DATA_COUNT(x) (((x) & 0xf) << 0)
418 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
419 #define AUX_TX_COMM_MASK (0xf << 0)
420 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
421 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
422 #define AUX_TX_COMM_MOT (0x1 << 2)
423 #define AUX_TX_COMM_WRITE (0x0 << 0)
424 #define AUX_TX_COMM_READ (0x1 << 0)
427 #define PD_AUX_IDLE (0x1 << 3)
428 #define ADDR_ONLY (0x1 << 1)
429 #define AUX_EN (0x1 << 0)
432 #define RST_DP_TX (0x1 << 0)
435 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4)
438 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
439 #define VCO_BIT_600_MICRO (0x5 << 0)
442 #define PD_RING_OSC (0x1 << 6)
443 #define AUX_TERMINAL_CTRL_37_5_OHM (0x0 << 4)
444 #define AUX_TERMINAL_CTRL_45_OHM (0x1 << 4)
445 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
446 #define AUX_TERMINAL_CTRL_65_OHM (0x3 << 4)
447 #define TX_CUR1_2X (0x1 << 2)
448 #define TX_CUR_16_MA (0x3 << 0)
451 #define DPCD_DPCD_REV (0x0000)
452 #define DPCD_MAX_LINK_RATE (0x0001)
453 #define DPCD_MAX_LANE_COUNT (0x0002)
454 #define DP_MAX_LANE_COUNT_MASK 0x1f
458 #define DPCD_LINK_BW_SET (0x0100)
459 #define DPCD_LANE_COUNT_SET (0x0101)
461 #define DPCD_TRAINING_PATTERN_SET (0x0102)
462 #define DP_TRAINING_PATTERN_DISABLE 0
466 #define DP_TRAINING_PATTERN_MASK 0x3
468 #define DPCD_TRAINING_LANE0_SET (0x0103)
469 #define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
470 #define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
472 #define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
473 #define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
474 #define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
475 #define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
478 #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
486 #define DPCD_LANE0_1_STATUS (0x0202)
487 #define DPCD_LANE2_3_STATUS (0x0203)
488 #define DP_LANE_CR_DONE (1 << 0)
495 #define DPCD_LANE_ALIGN_STATUS_UPDATED (0x0204)
496 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
500 #define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
501 #define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
502 #define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
503 #define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
504 #define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
506 #define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
508 #define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
511 #define DPCD_TEST_REQUEST (0x0218)
512 #define DPCD_TEST_RESPONSE (0x0260)
513 #define DPCD_TEST_EDID_CHECKSUM (0x0261)
514 #define DPCD_LINK_POWER_STATE (0x0600)
515 #define DP_SET_POWER_D0 0x1
516 #define DP_SET_POWER_D3 0x2
517 #define DP_SET_POWER_MASK 0x3
519 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
520 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
521 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
527 #define EDID_ADDR 0x50
528 #define EDID_LENGTH 0x80
529 #define EDID_HEADER 0x00
530 #define EDID_EXTENSION_FLAG 0x7e
587 LINK_RATE_1_62GBPS = 0x06,
588 LINK_RATE_2_70GBPS = 0x0a