Lines Matching +full:0 +full:x1
10 #define SD_EXTERNAL_CONFIG0_REG 0
16 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
19 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
31 (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
33 #define SD_EXTERNAL_CONFIG1_REG 0x4
36 (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
39 (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
42 (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
45 (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
47 #define SD_EXTERNAL_CONFIG2_REG 0x8
50 (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
53 (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
55 #define SD_EXTERNAL_STATUS0_REG 0x18
58 (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
61 (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
64 (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
67 (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
70 #define HPIPE_PWR_PLL_REG 0x4
71 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
73 (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
76 (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
78 #define HPIPE_KVCO_CALIB_CTRL_REG 0x8
81 (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
83 #define HPIPE_CAL_REG1_REG 0xc
86 (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
89 (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
91 #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
93 #define HPIPE_DFE_REG0 0x01C
96 (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
98 #define HPIPE_DFE_F3_F5_REG 0x028
101 (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
104 (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
106 #define HPIPE_G1_SET_0_REG 0x034
109 (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
112 (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
115 (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
118 (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
120 #define HPIPE_G1_SET_1_REG 0x038
121 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
123 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
126 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
129 (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
132 (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
135 (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
139 (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
141 #define HPIPE_G2_SET_0_REG 0x3c
144 (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
147 (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
150 (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
153 (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
155 #define HPIPE_G2_SET_1_REG 0x040
156 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
158 (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
161 (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
164 (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
167 (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
170 (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
173 (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
175 #define HPIPE_G3_SET_0_REG 0x44
178 (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
181 (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
184 (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
187 (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
190 (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
193 (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
195 #define HPIPE_G3_SET_1_REG 0x048
196 #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
198 (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
201 (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
204 (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
207 (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
210 (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
213 (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
216 (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
218 #define HPIPE_LOOPBACK_REG 0x08c
221 (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
223 #define HPIPE_SYNC_PATTERN_REG 0x090
226 (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET)
229 (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET)
231 #define HPIPE_INTERFACE_REG 0x94
234 (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
237 (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
240 (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
242 #define HPIPE_ISOLATE_MODE_REG 0x98
243 #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
245 (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
248 (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
250 #define HPIPE_G1_SET_2_REG 0xf4
251 #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
253 (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
256 (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
258 #define HPIPE_VTHIMPCAL_CTRL_REG 0x104
260 #define HPIPE_VDD_CAL_CTRL_REG 0x114
263 (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
265 #define HPIPE_VDD_CAL_0_REG 0x108
268 (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
270 #define HPIPE_PCIE_REG0 0x120
273 (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
276 (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
278 #define HPIPE_LANE_ALIGN_REG 0x124
281 (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
283 #define HPIPE_MISC_REG 0x13C
286 (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
289 (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
292 (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
295 (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
298 (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
300 #define HPIPE_RX_CONTROL_1_REG 0x140
303 (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
306 (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
308 #define HPIPE_PWR_CTR_REG 0x148
309 #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
311 (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
314 (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
316 #define HPIPE_SPD_DIV_FORCE_REG 0x154
319 (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
322 (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
325 (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
328 (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
331 (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
333 #define HPIPE_PLLINTP_REG1 0x150
335 #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
338 (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
341 (0x1 << HPIPE_SMAPLER_OFFSET)
343 #define HPIPE_TX_REG1_REG 0x174
346 (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
349 (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
351 #define HPIPE_PWR_CTR_DTL_REG 0x184
352 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
354 (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
357 (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
360 (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
363 (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
366 (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
369 (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
374 #define HPIPE_PHASE_CONTROL_REG 0x188
375 #define HPIPE_OS_PH_OFFSET_OFFSET 0
377 (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
380 (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
383 (0x1 << HPIPE_OS_PH_VALID_OFFSET)
385 #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
386 #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
388 (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
390 #define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
393 (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
395 #define HPIPE_DME_REG 0x228
398 (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
400 #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
403 (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
405 #define HPIPE_TX_TRAIN_CTRL_REG 0x26C
406 #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
408 (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
411 (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
414 (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
416 #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
417 #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
419 (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
421 #define HPIPE_PCIE_REG1 0x288
422 #define HPIPE_PCIE_REG3 0x290
424 #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
425 #define HPIPE_RX_TRAIN_TIMER_OFFSET 0
427 (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
430 (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
433 (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
436 (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
439 (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
441 #define HPIPE_TX_TRAIN_REG 0x31C
444 (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
447 (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
450 (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
453 (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
455 #define HPIPE_CDR_CONTROL_REG 0x418
458 (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
461 (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
464 (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
466 #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
469 (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
472 (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
475 (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
477 #define HPIPE_G1_SETTINGS_3_REG 0x440
478 #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
480 (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
483 (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
486 (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
489 (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
492 (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
495 (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
497 #define HPIPE_G1_SETTINGS_4_REG 0x444
500 (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
502 #define HPIPE_G2_SETTINGS_3_REG 0x448
504 #define HPIPE_G2_SETTINGS_4_REG 0x44c
507 (0x3 << HPIPE_G2_DFE_RES_OFFSET)
509 #define HPIPE_G3_SETTING_3_REG 0x450
510 #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
512 (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
515 (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
518 (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
521 (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
524 (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
526 #define HPIPE_G3_SETTING_4_REG 0x454
529 (0x3 << HPIPE_G3_DFE_RES_OFFSET)
531 #define HPIPE_TX_PRESET_INDEX_REG 0x468
532 #define HPIPE_TX_PRESET_INDEX_OFFSET 0
534 (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
536 #define HPIPE_DFE_CONTROL_REG 0x470
539 (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
541 #define HPIPE_DFE_CTRL_28_REG 0x49C
544 (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
546 #define HPIPE_G1_SETTING_5_REG 0x538
547 #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
549 (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
551 #define HPIPE_G3_SETTING_5_REG 0x548
552 #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
554 (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
556 #define HPIPE_LANE_CONFIG0_REG 0x600
557 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
559 (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
561 #define HPIPE_LANE_CONFIG1_REG 0x604
564 (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
567 (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
569 #define HPIPE_LANE_STATUS1_REG 0x60C
570 #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
572 (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
574 #define HPIPE_LANE_CFG4_REG 0x620
575 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
577 (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
580 (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
583 (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
586 (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
588 #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
591 (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
593 #define HPIPE_LANE_EQ_CFG1_REG 0x6a0
596 (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
598 #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
599 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
601 (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
604 (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
607 (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
609 #define HPIPE_RST_CLK_CTRL_REG 0x704
610 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
612 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
615 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
618 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
621 (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
623 #define HPIPE_TST_MODE_CTRL_REG 0x708
626 (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
628 #define HPIPE_CLK_SRC_LO_REG 0x70c
631 (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
634 (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
637 (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
639 #define HPIPE_CLK_SRC_HI_REG 0x710
640 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
642 (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
645 (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
648 (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
651 (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
653 #define HPIPE_GLOBAL_MISC_CTRL 0x718
654 #define HPIPE_GLOBAL_PM_CTRL 0x740
655 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
657 (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)