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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm8250-pinctrl.yaml70 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
116 reg = <0x0f100000 0x300000>,
117 <0x0f500000 0x300000>,
118 <0x0f900000 0x300000>;
125 gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
H A Dqcom,sdx75-tlmm.yaml66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
110 reg = <0x0f100000 0x300000>;
113 gpio-ranges = <&tlmm 0 0 133>;
H A Dqcom,sm8450-tlmm.yaml74 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
115 reg = <0x0f100000 0x300000>;
118 gpio-ranges = <&tlmm 0 0 211>;
H A Dqcom,sdx55-pinctrl.yaml59 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
112 reg = <0x0f100000 0x300000>;
115 gpio-ranges = <&tlmm 0 0 108>;
H A Dqcom,sc8280xp-tlmm.yaml67 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
116 reg = <0x0f100000 0x300000>;
122 gpio-ranges = <&tlmm 0 0 230>;
H A Dqcom,sm8350-tlmm.yaml74 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$"
116 reg = <0x0f100000 0x300000>;
122 gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */
H A Dqcom,sm8550-tlmm.yaml66 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
127 reg = <0x0f100000 0x300000>;
130 gpio-ranges = <&tlmm 0 0 211>;
H A Dqcom,sm6350-tlmm.yaml75 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
120 reg = <0x0f100000 0x300000>;
135 gpio-ranges = <&tlmm 0 0 157>;
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8026-samsung-matisse-wifi.dts35 reg = <0x03200000 0x800000>;
88 pinctrl-0 = <&backlight_i2c_default_state>;
94 #size-cells = <0>;
98 reg = <0x2c>;
100 dev-ctrl = /bits/ 8 <0x80>;
101 init-brt = /bits/ 8 <0x3f>;
103 pwms = <&backlight_pwm 0 100000>;
107 rom-addr = /bits/ 8 <0xa0>;
108 rom-val = /bits/ 8 <0x44>;
112 rom-addr = /bits/ 8 <0xa1>;
[all …]
/openbmc/linux/drivers/video/fbdev/geode/
H A Dvideo_gx.c34 { 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
35 { 39721, 0, 0x00000037 }, /* 25.1750 */
36 { 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
37 { 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
38 { 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
39 { 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
40 { 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
41 { 22271, 0, 0x00000063 }, /* 44.9000 */
42 { 20202, 0, 0x0000054B }, /* 49.5000 */
43 { 20000, 0, 0x0000026E }, /* 50.0000 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
42 reg = <0x0 0x43000000 0x0 0x20000>;
45 ranges = <0x0 0x0 0x43000000 0x20000>;
49 reg = <0x00000014 0x4>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi36 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
52 CPU0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi36 #clock-cells = <0>;
41 #clock-cells = <0>;
45 #clock-cells = <0>;
53 #clock-cells = <0>;
62 #clock-cells = <0>;
68 #size-cells = <0>;
70 CPU0: cpu@0 {
73 reg = <0 0>;
74 clocks = <&cpufreq_hw 0>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8450.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
77 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7280.dtsi78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x600000>;
104 reg = <0x0 0x80600000 0x0 0x200000>;
109 reg = <0x0 0x80800000 0x0 0x60000>;
114 reg = <0x0 0x80860000 0x0 0x20000>;
120 reg = <0x0 0x80884000 0x0 0x10000>;
125 reg = <0x0 0x808ff000 0x0 0x1000>;
130 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]