1*1dc3f881SRohit Agarwal# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*1dc3f881SRohit Agarwal%YAML 1.2 3*1dc3f881SRohit Agarwal--- 4*1dc3f881SRohit Agarwal$id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml# 5*1dc3f881SRohit Agarwal$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1dc3f881SRohit Agarwal 7*1dc3f881SRohit Agarwaltitle: Qualcomm Technologies, Inc. SDX75 TLMM block 8*1dc3f881SRohit Agarwal 9*1dc3f881SRohit Agarwalmaintainers: 10*1dc3f881SRohit Agarwal - Rohit Agarwal <quic_rohiagar@quicinc.com> 11*1dc3f881SRohit Agarwal 12*1dc3f881SRohit Agarwaldescription: 13*1dc3f881SRohit Agarwal Top Level Mode Multiplexer pin controller in Qualcomm SDX75 SoC. 14*1dc3f881SRohit Agarwal 15*1dc3f881SRohit AgarwalallOf: 16*1dc3f881SRohit Agarwal - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17*1dc3f881SRohit Agarwal 18*1dc3f881SRohit Agarwalproperties: 19*1dc3f881SRohit Agarwal compatible: 20*1dc3f881SRohit Agarwal const: qcom,sdx75-tlmm 21*1dc3f881SRohit Agarwal 22*1dc3f881SRohit Agarwal reg: 23*1dc3f881SRohit Agarwal maxItems: 1 24*1dc3f881SRohit Agarwal 25*1dc3f881SRohit Agarwal interrupts: true 26*1dc3f881SRohit Agarwal interrupt-controller: true 27*1dc3f881SRohit Agarwal "#interrupt-cells": true 28*1dc3f881SRohit Agarwal gpio-controller: true 29*1dc3f881SRohit Agarwal 30*1dc3f881SRohit Agarwal gpio-reserved-ranges: 31*1dc3f881SRohit Agarwal minItems: 1 32*1dc3f881SRohit Agarwal maxItems: 67 33*1dc3f881SRohit Agarwal 34*1dc3f881SRohit Agarwal gpio-line-names: 35*1dc3f881SRohit Agarwal maxItems: 133 36*1dc3f881SRohit Agarwal 37*1dc3f881SRohit Agarwal "#gpio-cells": true 38*1dc3f881SRohit Agarwal gpio-ranges: true 39*1dc3f881SRohit Agarwal wakeup-parent: true 40*1dc3f881SRohit Agarwal 41*1dc3f881SRohit AgarwalpatternProperties: 42*1dc3f881SRohit Agarwal "-state$": 43*1dc3f881SRohit Agarwal oneOf: 44*1dc3f881SRohit Agarwal - $ref: "#/$defs/qcom-sdx75-tlmm-state" 45*1dc3f881SRohit Agarwal - patternProperties: 46*1dc3f881SRohit Agarwal "-pins$": 47*1dc3f881SRohit Agarwal $ref: "#/$defs/qcom-sdx75-tlmm-state" 48*1dc3f881SRohit Agarwal additionalProperties: false 49*1dc3f881SRohit Agarwal 50*1dc3f881SRohit Agarwal$defs: 51*1dc3f881SRohit Agarwal qcom-sdx75-tlmm-state: 52*1dc3f881SRohit Agarwal type: object 53*1dc3f881SRohit Agarwal description: 54*1dc3f881SRohit Agarwal Pinctrl node's client devices use subnodes for desired pin configuration. 55*1dc3f881SRohit Agarwal Client device subnodes use below standard properties. 56*1dc3f881SRohit Agarwal $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 57*1dc3f881SRohit Agarwal unevaluatedProperties: false 58*1dc3f881SRohit Agarwal 59*1dc3f881SRohit Agarwal properties: 60*1dc3f881SRohit Agarwal pins: 61*1dc3f881SRohit Agarwal description: 62*1dc3f881SRohit Agarwal List of gpio pins affected by the properties specified in this 63*1dc3f881SRohit Agarwal subnode. 64*1dc3f881SRohit Agarwal items: 65*1dc3f881SRohit Agarwal oneOf: 66*1dc3f881SRohit Agarwal - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$" 67*1dc3f881SRohit Agarwal - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ] 68*1dc3f881SRohit Agarwal minItems: 1 69*1dc3f881SRohit Agarwal maxItems: 36 70*1dc3f881SRohit Agarwal 71*1dc3f881SRohit Agarwal function: 72*1dc3f881SRohit Agarwal description: 73*1dc3f881SRohit Agarwal Specify the alternative function to be configured for the specified 74*1dc3f881SRohit Agarwal pins. 75*1dc3f881SRohit Agarwal enum: [ adsp_ext, atest_char, audio_ref_clk, bimc_dte, char_exec, coex_uart2, 76*1dc3f881SRohit Agarwal coex_uart, cri_trng, cri_trng0, cri_trng1, dbg_out_clk, ddr_bist, 77*1dc3f881SRohit Agarwal ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, ebi2_lcd_te, emac0_mcg, 78*1dc3f881SRohit Agarwal emac0_ptp, emac1_mcg, emac1_ptp, emac_cdc, emac_pps_in, eth0_mdc, 79*1dc3f881SRohit Agarwal eth0_mdio, eth1_mdc, eth1_mdio, ext_dbg, gcc_125_clk, gcc_gp1_clk, 80*1dc3f881SRohit Agarwal gcc_gp2_clk, gcc_gp3_clk, gcc_plltest, gpio, i2s_mclk, jitter_bist, 81*1dc3f881SRohit Agarwal ldo_en, ldo_update, m_voc, mgpi_clk, native_char, native_tsens, 82*1dc3f881SRohit Agarwal native_tsense, nav_dr_sync, nav_gpio, pa_indicator, pci_e, 83*1dc3f881SRohit Agarwal pcie0_clkreq_n, pcie1_clkreq_n, pcie2_clkreq_n, pll_bist_sync, 84*1dc3f881SRohit Agarwal pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, 85*1dc3f881SRohit Agarwal qlink0_b_en, qlink0_b_req, qlink0_l_en, qlink0_l_req, qlink0_wmss, 86*1dc3f881SRohit Agarwal qlink1_l_en, qlink1_l_req, qlink1_wmss, qup_se0, qup_se1_l2_mira, 87*1dc3f881SRohit Agarwal qup_se1_l2_mirb, qup_se1_l3_mira, qup_se1_l3_mirb, qup_se2, qup_se3, 88*1dc3f881SRohit Agarwal qup_se4, qup_se5, qup_se6, qup_se7, qup_se8, rgmii_rx_ctl, rgmii_rxc, 89*1dc3f881SRohit Agarwal rgmii_rxd, rgmii_tx_ctl, rgmii_txc, rgmii_txd, sd_card, sdc1_tb, 90*1dc3f881SRohit Agarwal sdc2_tb_trig, sec_mi2s, sgmii_phy_intr0_n, sgmii_phy_intr1_n, 91*1dc3f881SRohit Agarwal spmi_coex, spmi_vgi, tgu_ch0_trigout, tmess_prng0, tmess_prng1, 92*1dc3f881SRohit Agarwal tmess_prng2, tmess_prng3, tri_mi2s, uim1_clk, uim1_data, uim1_present, 93*1dc3f881SRohit Agarwal uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, 94*1dc3f881SRohit Agarwal usb2phy_ac_en, vsense_trigger_mirnat] 95*1dc3f881SRohit Agarwal 96*1dc3f881SRohit Agarwal required: 97*1dc3f881SRohit Agarwal - pins 98*1dc3f881SRohit Agarwal 99*1dc3f881SRohit Agarwalrequired: 100*1dc3f881SRohit Agarwal - compatible 101*1dc3f881SRohit Agarwal - reg 102*1dc3f881SRohit Agarwal 103*1dc3f881SRohit AgarwaladditionalProperties: false 104*1dc3f881SRohit Agarwal 105*1dc3f881SRohit Agarwalexamples: 106*1dc3f881SRohit Agarwal - | 107*1dc3f881SRohit Agarwal #include <dt-bindings/interrupt-controller/arm-gic.h> 108*1dc3f881SRohit Agarwal tlmm: pinctrl@f100000 { 109*1dc3f881SRohit Agarwal compatible = "qcom,sdx75-tlmm"; 110*1dc3f881SRohit Agarwal reg = <0x0f100000 0x300000>; 111*1dc3f881SRohit Agarwal gpio-controller; 112*1dc3f881SRohit Agarwal #gpio-cells = <2>; 113*1dc3f881SRohit Agarwal gpio-ranges = <&tlmm 0 0 133>; 114*1dc3f881SRohit Agarwal interrupt-controller; 115*1dc3f881SRohit Agarwal #interrupt-cells = <2>; 116*1dc3f881SRohit Agarwal interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 117*1dc3f881SRohit Agarwal 118*1dc3f881SRohit Agarwal gpio-wo-state { 119*1dc3f881SRohit Agarwal pins = "gpio1"; 120*1dc3f881SRohit Agarwal function = "gpio"; 121*1dc3f881SRohit Agarwal }; 122*1dc3f881SRohit Agarwal 123*1dc3f881SRohit Agarwal uart-w-state { 124*1dc3f881SRohit Agarwal rx-pins { 125*1dc3f881SRohit Agarwal pins = "gpio12"; 126*1dc3f881SRohit Agarwal function = "qup_se1_l2_mira"; 127*1dc3f881SRohit Agarwal bias-disable; 128*1dc3f881SRohit Agarwal }; 129*1dc3f881SRohit Agarwal 130*1dc3f881SRohit Agarwal tx-pins { 131*1dc3f881SRohit Agarwal pins = "gpio13"; 132*1dc3f881SRohit Agarwal function = "qup_se1_l3_mira"; 133*1dc3f881SRohit Agarwal bias-disable; 134*1dc3f881SRohit Agarwal }; 135*1dc3f881SRohit Agarwal }; 136*1dc3f881SRohit Agarwal }; 137*1dc3f881SRohit Agarwal... 138