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/openbmc/linux/arch/powerpc/boot/dts/
H A Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-am64.dtsi53 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
57 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
58 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
59 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
60 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
62 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
H A Dk3-j784s4.dtsi26 #size-cells = <0>;
65 cpu0: cpu@0 {
67 reg = <0x000>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
81 reg = <0x001>;
84 i-cache-size = <0xc000>;
87 d-cache-size = <0x8000>;
95 reg = <0x002>;
98 i-cache-size = <0xc000>;
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
42 reg = <0x0 0x43000000 0x0 0x20000>;
45 ranges = <0x0 0x0 0x43000000 0x20000>;
49 reg = <0x00000014 0x4>;
[all …]
/openbmc/linux/arch/sh/configs/
H A Dhp6xx_defconfig8 CONFIG_MEMORY_START=0x0d000000
9 CONFIG_MEMORY_SIZE=0x00400000
/openbmc/linux/arch/xtensa/boot/dts/
H A Dcsp.dts11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
14 memory@0 {
16 reg = <0x00000000 0x40000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
36 #clock-cells = <0>;
45 ranges = <0x00000000 0xf0000000 0x10000000>;
47 uart0: serial@0d000000 {
51 reg = <0x0d000000 0x1000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-ep.yaml94 reg = <0x00 0x02900000 0x00 0x1000>,
95 <0x00 0x02907000 0x00 0x400>,
96 <0x00 0x0d000000 0x00 0x00800000>,
97 <0x00 0x10000000 0x00 0x08000000>;
99 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
H A Dti,j721e-pci-host.yaml66 const: 0x104c
70 - 0xb00d
71 - 0xb00f
72 - 0xb010
73 - 0xb013
129 reg = <0x00 0x02900000 0x00 0x1000>,
130 <0x00 0x02907000 0x00 0x400>,
131 <0x00 0x0d000000 0x00 0x00800000>,
132 <0x00 0x10000000 0x00 0x00001000>;
134 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
[all …]
H A Dsnps,dw-pcie.yaml55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
83 normally mapped to the 0x0 address of this region, while eDMA
84 is available at 0x80000 base address.
149 pattern: '^dma([0-9]|1[0-5])?$'
222 reg = <0xdfc00000 0x0001000>, /* IP registers */
223 <0xd0000000 0x0002000>; /* Configuration space */
227 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
228 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/openbmc/qemu/linux-user/include/host/aarch64/
H A Dhost-signal.h19 #define ESR_MAGIC 0x45535201
62 /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ in host_signal_write()
63 return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1; in host_signal_write()
73 return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ in host_signal_write()
74 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ in host_signal_write()
75 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ in host_signal_write()
76 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ in host_signal_write()
77 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ in host_signal_write()
78 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ in host_signal_write()
79 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */ in host_signal_write()
[all …]
/openbmc/linux/arch/arm/nwfpe/
H A Dentry.S50 EmulateAll returns 1 if the emulation was successful, or 0 if not.
83 cmp r0, #0 @ was emulation successful
91 and r2, r6, #0x0F000000 @ test for FP insns
92 teq r2, #0x0C000000
93 teqne r2, #0x0D000000
94 teqne r2, #0x0E000000
138 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
140 and r8, r0, #0x00000f00 @ mask out CP number
144 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
152 ret lr @ CP#0
/openbmc/linux/arch/powerpc/platforms/embedded6xx/
H A Dusbgecko_udbg.c23 #define EXI_CSR 0x00
24 #define EXI_CSR_CLKMASK (0x7<<4)
26 #define EXI_CSR_CSMASK (0x7<<7)
27 #define EXI_CSR_CS_0 (0x1<<7) /* Chip Select 001 */
29 #define EXI_CR 0x0c
30 #define EXI_CR_TSTART (1<<0)
35 #define EXI_DATA 0x10
67 out_be32(csr_reg, 0); in ug_io_transaction()
81 return 0; in ug_is_adapter_present()
83 return ug_io_transaction(0x90000000) == 0x04700000; in ug_is_adapter_present()
[all …]
/openbmc/linux/drivers/crypto/chelsio/
H A Dchcr_crypto.h63 #define CHCR_ENCRYPT_OP 0
72 #define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
75 #define CHCR_SCMD_CIPHER_MODE_NOP 0
83 #define CHCR_SCMD_AUTH_MODE_NOP 0
95 #define CHCR_SCMD_HMAC_CTRL_NOP 0
103 #define VERIFY_HW 0
106 #define CHCR_SCMD_IVGEN_CTRL_HW 0
111 #define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
116 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
128 #define IV_NOP 0
[all …]
/openbmc/qemu/contrib/plugins/
H A Dhowvec.c25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS},
72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/openbmc/linux/arch/mips/alchemy/devboards/
H A Ddb1000.c49 return 0; in db1000_board_setup()
56 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
59 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
74 [0] = {
76 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
88 .id = 0,
99 [0] = {
101 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
113 .id = 0,
123 [0] = {
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dstate_hi.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
54 #define VIVS_HI 0x00000000
56 #define VIVS_HI_CLOCK_CONTROL 0x00000000
[all …]
/openbmc/linux/sound/soc/sh/
H A Dsiu_dai.c24 # define SIU_MAX_VOLUME 0x1000
26 # define SIU_MAX_VOLUME 0x7fff
29 #define PRAM_SIZE 0x2000
30 #define XRAM_SIZE 0x800
31 #define YRAM_SIZE 0x800
33 #define XRAM_OFFSET 0x4000
34 #define YRAM_OFFSET 0x6000
35 #define REG_OFFSET 0xc000
40 #define VOLUME_CAPTURE 0
42 #define DFLT_VOLUME_LEVEL 0x08000800
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra210.dtsi17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29 bus-range = <0x00 0xff>;
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]

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