1fd534e9bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2f59c811fSManuel Lauss /*
3851d4f5dSManuel Lauss * DBAu1000/1500/1100 PBAu1100/1500 board support
4f59c811fSManuel Lauss *
5f59c811fSManuel Lauss * Copyright 2000, 2008 MontaVista Software Inc.
6f59c811fSManuel Lauss * Author: MontaVista Software, Inc. <source@mvista.com>
7f59c811fSManuel Lauss */
8f59c811fSManuel Lauss
96b1889c1SManuel Lauss #include <linux/clk.h>
10f59c811fSManuel Lauss #include <linux/dma-mapping.h>
11f59c811fSManuel Lauss #include <linux/gpio.h>
129b00bc7bSLinus Walleij #include <linux/gpio/machine.h>
13f59c811fSManuel Lauss #include <linux/init.h>
14f59c811fSManuel Lauss #include <linux/interrupt.h>
15c9af5144SManuel Lauss #include <linux/leds.h>
16c9af5144SManuel Lauss #include <linux/mmc/host.h>
17f59c811fSManuel Lauss #include <linux/platform_device.h>
18f59c811fSManuel Lauss #include <linux/pm.h>
192a32daf1SManuel Lauss #include <linux/spi/spi.h>
202a32daf1SManuel Lauss #include <linux/spi/spi_gpio.h>
212a32daf1SManuel Lauss #include <linux/spi/ads7846.h>
22f59c811fSManuel Lauss #include <asm/mach-au1x00/au1000.h>
23832f5dacSAlban Bedel #include <asm/mach-au1x00/gpio-au1000.h>
24f59c811fSManuel Lauss #include <asm/mach-au1x00/au1000_dma.h>
25c9af5144SManuel Lauss #include <asm/mach-au1x00/au1100_mmc.h>
26f59c811fSManuel Lauss #include <asm/mach-db1x00/bcsr.h>
27f59c811fSManuel Lauss #include <asm/reboot.h>
28f59c811fSManuel Lauss #include <prom.h>
29f59c811fSManuel Lauss #include "platform.h"
30f59c811fSManuel Lauss
31f59c811fSManuel Lauss #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
32f59c811fSManuel Lauss
33970e268dSManuel Lauss const char *get_system_type(void);
34f59c811fSManuel Lauss
db1000_board_setup(void)35970e268dSManuel Lauss int __init db1000_board_setup(void)
36f59c811fSManuel Lauss {
37f59c811fSManuel Lauss /* initialize board register space */
38f59c811fSManuel Lauss bcsr_init(DB1000_BCSR_PHYS_ADDR,
39f59c811fSManuel Lauss DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
40f59c811fSManuel Lauss
41970e268dSManuel Lauss switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
42970e268dSManuel Lauss case BCSR_WHOAMI_DB1000:
43970e268dSManuel Lauss case BCSR_WHOAMI_DB1500:
44970e268dSManuel Lauss case BCSR_WHOAMI_DB1100:
45970e268dSManuel Lauss case BCSR_WHOAMI_PB1500:
46970e268dSManuel Lauss case BCSR_WHOAMI_PB1500R2:
47970e268dSManuel Lauss case BCSR_WHOAMI_PB1100:
48970e268dSManuel Lauss pr_info("AMD Alchemy %s Board\n", get_system_type());
49970e268dSManuel Lauss return 0;
50f59c811fSManuel Lauss }
51970e268dSManuel Lauss return -ENODEV;
52970e268dSManuel Lauss }
53f59c811fSManuel Lauss
db1500_map_pci_irq(const struct pci_dev * d,u8 slot,u8 pin)54f59c811fSManuel Lauss static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
55f59c811fSManuel Lauss {
56f59c811fSManuel Lauss if ((slot < 12) || (slot > 13) || pin == 0)
57f59c811fSManuel Lauss return -1;
58f59c811fSManuel Lauss if (slot == 12)
59f59c811fSManuel Lauss return (pin == 1) ? AU1500_PCI_INTA : 0xff;
60f59c811fSManuel Lauss if (slot == 13) {
61f59c811fSManuel Lauss switch (pin) {
62f59c811fSManuel Lauss case 1: return AU1500_PCI_INTA;
63f59c811fSManuel Lauss case 2: return AU1500_PCI_INTB;
64f59c811fSManuel Lauss case 3: return AU1500_PCI_INTC;
65f59c811fSManuel Lauss case 4: return AU1500_PCI_INTD;
66f59c811fSManuel Lauss }
67f59c811fSManuel Lauss }
68f59c811fSManuel Lauss return -1;
69f59c811fSManuel Lauss }
70f59c811fSManuel Lauss
71994bc7faSManuel Lauss static u64 au1xxx_all_dmamask = DMA_BIT_MASK(32);
72994bc7faSManuel Lauss
73f59c811fSManuel Lauss static struct resource alchemy_pci_host_res[] = {
74f59c811fSManuel Lauss [0] = {
75f59c811fSManuel Lauss .start = AU1500_PCI_PHYS_ADDR,
76f59c811fSManuel Lauss .end = AU1500_PCI_PHYS_ADDR + 0xfff,
77f59c811fSManuel Lauss .flags = IORESOURCE_MEM,
78f59c811fSManuel Lauss },
79f59c811fSManuel Lauss };
80f59c811fSManuel Lauss
81f59c811fSManuel Lauss static struct alchemy_pci_platdata db1500_pci_pd = {
82f59c811fSManuel Lauss .board_map_irq = db1500_map_pci_irq,
83f59c811fSManuel Lauss };
84f59c811fSManuel Lauss
85f59c811fSManuel Lauss static struct platform_device db1500_pci_host_dev = {
86f59c811fSManuel Lauss .dev.platform_data = &db1500_pci_pd,
87f59c811fSManuel Lauss .name = "alchemy-pci",
88f59c811fSManuel Lauss .id = 0,
89f59c811fSManuel Lauss .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
90f59c811fSManuel Lauss .resource = alchemy_pci_host_res,
91f59c811fSManuel Lauss };
92f59c811fSManuel Lauss
db1500_pci_setup(void)93970e268dSManuel Lauss int __init db1500_pci_setup(void)
94f59c811fSManuel Lauss {
95f59c811fSManuel Lauss return platform_device_register(&db1500_pci_host_dev);
96f59c811fSManuel Lauss }
97f59c811fSManuel Lauss
98f59c811fSManuel Lauss static struct resource au1100_lcd_resources[] = {
99f59c811fSManuel Lauss [0] = {
100f59c811fSManuel Lauss .start = AU1100_LCD_PHYS_ADDR,
101f59c811fSManuel Lauss .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
102f59c811fSManuel Lauss .flags = IORESOURCE_MEM,
103f59c811fSManuel Lauss },
104f59c811fSManuel Lauss [1] = {
105f59c811fSManuel Lauss .start = AU1100_LCD_INT,
106f59c811fSManuel Lauss .end = AU1100_LCD_INT,
107f59c811fSManuel Lauss .flags = IORESOURCE_IRQ,
108f59c811fSManuel Lauss }
109f59c811fSManuel Lauss };
110f59c811fSManuel Lauss
111f59c811fSManuel Lauss static struct platform_device au1100_lcd_device = {
112f59c811fSManuel Lauss .name = "au1100-lcd",
113f59c811fSManuel Lauss .id = 0,
114f59c811fSManuel Lauss .dev = {
115994bc7faSManuel Lauss .dma_mask = &au1xxx_all_dmamask,
116f59c811fSManuel Lauss .coherent_dma_mask = DMA_BIT_MASK(32),
117f59c811fSManuel Lauss },
118f59c811fSManuel Lauss .num_resources = ARRAY_SIZE(au1100_lcd_resources),
119f59c811fSManuel Lauss .resource = au1100_lcd_resources,
120f59c811fSManuel Lauss };
121f59c811fSManuel Lauss
122f59c811fSManuel Lauss static struct resource alchemy_ac97c_res[] = {
123f59c811fSManuel Lauss [0] = {
124f59c811fSManuel Lauss .start = AU1000_AC97_PHYS_ADDR,
125f59c811fSManuel Lauss .end = AU1000_AC97_PHYS_ADDR + 0xfff,
126f59c811fSManuel Lauss .flags = IORESOURCE_MEM,
127f59c811fSManuel Lauss },
128f59c811fSManuel Lauss [1] = {
129f59c811fSManuel Lauss .start = DMA_ID_AC97C_TX,
130f59c811fSManuel Lauss .end = DMA_ID_AC97C_TX,
131f59c811fSManuel Lauss .flags = IORESOURCE_DMA,
132f59c811fSManuel Lauss },
133f59c811fSManuel Lauss [2] = {
134f59c811fSManuel Lauss .start = DMA_ID_AC97C_RX,
135f59c811fSManuel Lauss .end = DMA_ID_AC97C_RX,
136f59c811fSManuel Lauss .flags = IORESOURCE_DMA,
137f59c811fSManuel Lauss },
138f59c811fSManuel Lauss };
139f59c811fSManuel Lauss
140f59c811fSManuel Lauss static struct platform_device alchemy_ac97c_dev = {
141f59c811fSManuel Lauss .name = "alchemy-ac97c",
142f59c811fSManuel Lauss .id = -1,
143f59c811fSManuel Lauss .resource = alchemy_ac97c_res,
144f59c811fSManuel Lauss .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
145f59c811fSManuel Lauss };
146f59c811fSManuel Lauss
147f59c811fSManuel Lauss static struct platform_device alchemy_ac97c_dma_dev = {
148f59c811fSManuel Lauss .name = "alchemy-pcm-dma",
149f59c811fSManuel Lauss .id = 0,
150f59c811fSManuel Lauss };
151f59c811fSManuel Lauss
152f59c811fSManuel Lauss static struct platform_device db1x00_codec_dev = {
153f59c811fSManuel Lauss .name = "ac97-codec",
154f59c811fSManuel Lauss .id = -1,
155f59c811fSManuel Lauss };
156f59c811fSManuel Lauss
157f59c811fSManuel Lauss static struct platform_device db1x00_audio_dev = {
158f59c811fSManuel Lauss .name = "db1000-audio",
159994bc7faSManuel Lauss .dev = {
160994bc7faSManuel Lauss .dma_mask = &au1xxx_all_dmamask,
161994bc7faSManuel Lauss .coherent_dma_mask = DMA_BIT_MASK(32),
162994bc7faSManuel Lauss },
163f59c811fSManuel Lauss };
164f59c811fSManuel Lauss
165c9af5144SManuel Lauss /******************************************************************************/
166c9af5144SManuel Lauss
167*ef8f8f04SChristoph Hellwig #ifdef CONFIG_MMC_AU1X
db1100_mmc_cd(int irq,void * ptr)168c9af5144SManuel Lauss static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
169c9af5144SManuel Lauss {
170d4a5c59aSChristoph Hellwig mmc_detect_change(ptr, msecs_to_jiffies(500));
171c9af5144SManuel Lauss return IRQ_HANDLED;
172c9af5144SManuel Lauss }
173c9af5144SManuel Lauss
db1100_mmc_cd_setup(void * mmc_host,int en)174c9af5144SManuel Lauss static int db1100_mmc_cd_setup(void *mmc_host, int en)
175c9af5144SManuel Lauss {
176851d4f5dSManuel Lauss int ret = 0, irq;
177851d4f5dSManuel Lauss
178851d4f5dSManuel Lauss if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
179851d4f5dSManuel Lauss irq = AU1100_GPIO19_INT;
180851d4f5dSManuel Lauss else
181851d4f5dSManuel Lauss irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */
182c9af5144SManuel Lauss
183c9af5144SManuel Lauss if (en) {
184851d4f5dSManuel Lauss irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
185851d4f5dSManuel Lauss ret = request_irq(irq, db1100_mmc_cd, 0,
186c9af5144SManuel Lauss "sd0_cd", mmc_host);
187c9af5144SManuel Lauss } else
188851d4f5dSManuel Lauss free_irq(irq, mmc_host);
189c9af5144SManuel Lauss return ret;
190c9af5144SManuel Lauss }
191c9af5144SManuel Lauss
db1100_mmc1_cd_setup(void * mmc_host,int en)192c9af5144SManuel Lauss static int db1100_mmc1_cd_setup(void *mmc_host, int en)
193c9af5144SManuel Lauss {
194851d4f5dSManuel Lauss int ret = 0, irq;
195851d4f5dSManuel Lauss
196851d4f5dSManuel Lauss if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
197851d4f5dSManuel Lauss irq = AU1100_GPIO20_INT;
198851d4f5dSManuel Lauss else
199851d4f5dSManuel Lauss irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */
200c9af5144SManuel Lauss
201c9af5144SManuel Lauss if (en) {
202851d4f5dSManuel Lauss irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
203851d4f5dSManuel Lauss ret = request_irq(irq, db1100_mmc_cd, 0,
204c9af5144SManuel Lauss "sd1_cd", mmc_host);
205c9af5144SManuel Lauss } else
206851d4f5dSManuel Lauss free_irq(irq, mmc_host);
207c9af5144SManuel Lauss return ret;
208c9af5144SManuel Lauss }
209c9af5144SManuel Lauss
db1100_mmc_card_readonly(void * mmc_host)210c9af5144SManuel Lauss static int db1100_mmc_card_readonly(void *mmc_host)
211c9af5144SManuel Lauss {
212c9af5144SManuel Lauss /* testing suggests that this bit is inverted */
213c9af5144SManuel Lauss return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
214c9af5144SManuel Lauss }
215c9af5144SManuel Lauss
db1100_mmc_card_inserted(void * mmc_host)216c9af5144SManuel Lauss static int db1100_mmc_card_inserted(void *mmc_host)
217c9af5144SManuel Lauss {
218c9af5144SManuel Lauss return !alchemy_gpio_get_value(19);
219c9af5144SManuel Lauss }
220c9af5144SManuel Lauss
db1100_mmc_set_power(void * mmc_host,int state)221c9af5144SManuel Lauss static void db1100_mmc_set_power(void *mmc_host, int state)
222c9af5144SManuel Lauss {
223851d4f5dSManuel Lauss int bit;
224851d4f5dSManuel Lauss
225851d4f5dSManuel Lauss if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
226851d4f5dSManuel Lauss bit = BCSR_BOARD_SD0PWR;
227851d4f5dSManuel Lauss else
228851d4f5dSManuel Lauss bit = BCSR_BOARD_PB1100_SD0PWR;
229851d4f5dSManuel Lauss
230c9af5144SManuel Lauss if (state) {
231851d4f5dSManuel Lauss bcsr_mod(BCSR_BOARD, 0, bit);
232c9af5144SManuel Lauss msleep(400); /* stabilization time */
233c9af5144SManuel Lauss } else
234851d4f5dSManuel Lauss bcsr_mod(BCSR_BOARD, bit, 0);
235c9af5144SManuel Lauss }
236c9af5144SManuel Lauss
db1100_mmcled_set(struct led_classdev * led,enum led_brightness b)237c9af5144SManuel Lauss static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
238c9af5144SManuel Lauss {
239c9af5144SManuel Lauss if (b != LED_OFF)
240c9af5144SManuel Lauss bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
241c9af5144SManuel Lauss else
242c9af5144SManuel Lauss bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
243c9af5144SManuel Lauss }
244c9af5144SManuel Lauss
245c9af5144SManuel Lauss static struct led_classdev db1100_mmc_led = {
246c9af5144SManuel Lauss .brightness_set = db1100_mmcled_set,
247c9af5144SManuel Lauss };
248c9af5144SManuel Lauss
db1100_mmc1_card_readonly(void * mmc_host)249c9af5144SManuel Lauss static int db1100_mmc1_card_readonly(void *mmc_host)
250c9af5144SManuel Lauss {
251c9af5144SManuel Lauss return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
252c9af5144SManuel Lauss }
253c9af5144SManuel Lauss
db1100_mmc1_card_inserted(void * mmc_host)254c9af5144SManuel Lauss static int db1100_mmc1_card_inserted(void *mmc_host)
255c9af5144SManuel Lauss {
256c9af5144SManuel Lauss return !alchemy_gpio_get_value(20);
257c9af5144SManuel Lauss }
258c9af5144SManuel Lauss
db1100_mmc1_set_power(void * mmc_host,int state)259c9af5144SManuel Lauss static void db1100_mmc1_set_power(void *mmc_host, int state)
260c9af5144SManuel Lauss {
261851d4f5dSManuel Lauss int bit;
262851d4f5dSManuel Lauss
263851d4f5dSManuel Lauss if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
264851d4f5dSManuel Lauss bit = BCSR_BOARD_SD1PWR;
265851d4f5dSManuel Lauss else
266851d4f5dSManuel Lauss bit = BCSR_BOARD_PB1100_SD1PWR;
267851d4f5dSManuel Lauss
268c9af5144SManuel Lauss if (state) {
269851d4f5dSManuel Lauss bcsr_mod(BCSR_BOARD, 0, bit);
270c9af5144SManuel Lauss msleep(400); /* stabilization time */
271c9af5144SManuel Lauss } else
272851d4f5dSManuel Lauss bcsr_mod(BCSR_BOARD, bit, 0);
273c9af5144SManuel Lauss }
274c9af5144SManuel Lauss
db1100_mmc1led_set(struct led_classdev * led,enum led_brightness b)275c9af5144SManuel Lauss static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
276c9af5144SManuel Lauss {
277c9af5144SManuel Lauss if (b != LED_OFF)
278c9af5144SManuel Lauss bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
279c9af5144SManuel Lauss else
280c9af5144SManuel Lauss bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
281c9af5144SManuel Lauss }
282c9af5144SManuel Lauss
283c9af5144SManuel Lauss static struct led_classdev db1100_mmc1_led = {
284c9af5144SManuel Lauss .brightness_set = db1100_mmc1led_set,
285c9af5144SManuel Lauss };
286c9af5144SManuel Lauss
287c9af5144SManuel Lauss static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
288c9af5144SManuel Lauss [0] = {
289c9af5144SManuel Lauss .cd_setup = db1100_mmc_cd_setup,
290c9af5144SManuel Lauss .set_power = db1100_mmc_set_power,
291c9af5144SManuel Lauss .card_inserted = db1100_mmc_card_inserted,
292c9af5144SManuel Lauss .card_readonly = db1100_mmc_card_readonly,
293c9af5144SManuel Lauss .led = &db1100_mmc_led,
294c9af5144SManuel Lauss },
295c9af5144SManuel Lauss [1] = {
296c9af5144SManuel Lauss .cd_setup = db1100_mmc1_cd_setup,
297c9af5144SManuel Lauss .set_power = db1100_mmc1_set_power,
298c9af5144SManuel Lauss .card_inserted = db1100_mmc1_card_inserted,
299c9af5144SManuel Lauss .card_readonly = db1100_mmc1_card_readonly,
300c9af5144SManuel Lauss .led = &db1100_mmc1_led,
301c9af5144SManuel Lauss },
302c9af5144SManuel Lauss };
303c9af5144SManuel Lauss
304c9af5144SManuel Lauss static struct resource au1100_mmc0_resources[] = {
305c9af5144SManuel Lauss [0] = {
306c9af5144SManuel Lauss .start = AU1100_SD0_PHYS_ADDR,
307c9af5144SManuel Lauss .end = AU1100_SD0_PHYS_ADDR + 0xfff,
308c9af5144SManuel Lauss .flags = IORESOURCE_MEM,
309c9af5144SManuel Lauss },
310c9af5144SManuel Lauss [1] = {
311c9af5144SManuel Lauss .start = AU1100_SD_INT,
312c9af5144SManuel Lauss .end = AU1100_SD_INT,
313c9af5144SManuel Lauss .flags = IORESOURCE_IRQ,
314c9af5144SManuel Lauss },
315c9af5144SManuel Lauss [2] = {
316c9af5144SManuel Lauss .start = DMA_ID_SD0_TX,
317c9af5144SManuel Lauss .end = DMA_ID_SD0_TX,
318c9af5144SManuel Lauss .flags = IORESOURCE_DMA,
319c9af5144SManuel Lauss },
320c9af5144SManuel Lauss [3] = {
321c9af5144SManuel Lauss .start = DMA_ID_SD0_RX,
322c9af5144SManuel Lauss .end = DMA_ID_SD0_RX,
323c9af5144SManuel Lauss .flags = IORESOURCE_DMA,
324c9af5144SManuel Lauss }
325c9af5144SManuel Lauss };
326c9af5144SManuel Lauss
327c9af5144SManuel Lauss static struct platform_device db1100_mmc0_dev = {
328c9af5144SManuel Lauss .name = "au1xxx-mmc",
329c9af5144SManuel Lauss .id = 0,
330c9af5144SManuel Lauss .dev = {
331994bc7faSManuel Lauss .dma_mask = &au1xxx_all_dmamask,
332c9af5144SManuel Lauss .coherent_dma_mask = DMA_BIT_MASK(32),
333c9af5144SManuel Lauss .platform_data = &db1100_mmc_platdata[0],
334c9af5144SManuel Lauss },
335c9af5144SManuel Lauss .num_resources = ARRAY_SIZE(au1100_mmc0_resources),
336c9af5144SManuel Lauss .resource = au1100_mmc0_resources,
337c9af5144SManuel Lauss };
338c9af5144SManuel Lauss
339c9af5144SManuel Lauss static struct resource au1100_mmc1_res[] = {
340c9af5144SManuel Lauss [0] = {
341c9af5144SManuel Lauss .start = AU1100_SD1_PHYS_ADDR,
342c9af5144SManuel Lauss .end = AU1100_SD1_PHYS_ADDR + 0xfff,
343c9af5144SManuel Lauss .flags = IORESOURCE_MEM,
344c9af5144SManuel Lauss },
345c9af5144SManuel Lauss [1] = {
346c9af5144SManuel Lauss .start = AU1100_SD_INT,
347c9af5144SManuel Lauss .end = AU1100_SD_INT,
348c9af5144SManuel Lauss .flags = IORESOURCE_IRQ,
349c9af5144SManuel Lauss },
350c9af5144SManuel Lauss [2] = {
351c9af5144SManuel Lauss .start = DMA_ID_SD1_TX,
352c9af5144SManuel Lauss .end = DMA_ID_SD1_TX,
353c9af5144SManuel Lauss .flags = IORESOURCE_DMA,
354c9af5144SManuel Lauss },
355c9af5144SManuel Lauss [3] = {
356c9af5144SManuel Lauss .start = DMA_ID_SD1_RX,
357c9af5144SManuel Lauss .end = DMA_ID_SD1_RX,
358c9af5144SManuel Lauss .flags = IORESOURCE_DMA,
359c9af5144SManuel Lauss }
360c9af5144SManuel Lauss };
361c9af5144SManuel Lauss
362c9af5144SManuel Lauss static struct platform_device db1100_mmc1_dev = {
363c9af5144SManuel Lauss .name = "au1xxx-mmc",
364c9af5144SManuel Lauss .id = 1,
365c9af5144SManuel Lauss .dev = {
366994bc7faSManuel Lauss .dma_mask = &au1xxx_all_dmamask,
367c9af5144SManuel Lauss .coherent_dma_mask = DMA_BIT_MASK(32),
368c9af5144SManuel Lauss .platform_data = &db1100_mmc_platdata[1],
369c9af5144SManuel Lauss },
370c9af5144SManuel Lauss .num_resources = ARRAY_SIZE(au1100_mmc1_res),
371c9af5144SManuel Lauss .resource = au1100_mmc1_res,
372c9af5144SManuel Lauss };
373*ef8f8f04SChristoph Hellwig #endif /* CONFIG_MMC_AU1X */
374c9af5144SManuel Lauss
375e734ae13SManuel Lauss /******************************************************************************/
376e734ae13SManuel Lauss
3772a32daf1SManuel Lauss static struct ads7846_platform_data db1100_touch_pd = {
3782a32daf1SManuel Lauss .model = 7846,
3792a32daf1SManuel Lauss .vref_mv = 3300,
3802a32daf1SManuel Lauss };
3812a32daf1SManuel Lauss
3822a32daf1SManuel Lauss static struct spi_gpio_platform_data db1100_spictl_pd = {
3832a32daf1SManuel Lauss .num_chipselect = 1,
3842a32daf1SManuel Lauss };
3852a32daf1SManuel Lauss
386767d8336SLinus Walleij static struct gpiod_lookup_table db1100_touch_gpio_table = {
387767d8336SLinus Walleij .dev_id = "spi0.0",
388767d8336SLinus Walleij .table = {
389767d8336SLinus Walleij GPIO_LOOKUP("alchemy-gpio2", 21,
390767d8336SLinus Walleij "pendown", GPIO_ACTIVE_LOW),
391767d8336SLinus Walleij { }
392767d8336SLinus Walleij },
393767d8336SLinus Walleij };
394767d8336SLinus Walleij
3952a32daf1SManuel Lauss static struct spi_board_info db1100_spi_info[] __initdata = {
3962a32daf1SManuel Lauss [0] = {
3972a32daf1SManuel Lauss .modalias = "ads7846",
3982a32daf1SManuel Lauss .max_speed_hz = 3250000,
3992a32daf1SManuel Lauss .bus_num = 0,
4002a32daf1SManuel Lauss .chip_select = 0,
4012a32daf1SManuel Lauss .mode = 0,
4022a32daf1SManuel Lauss .irq = AU1100_GPIO21_INT,
4032a32daf1SManuel Lauss .platform_data = &db1100_touch_pd,
4042a32daf1SManuel Lauss },
4052a32daf1SManuel Lauss };
4062a32daf1SManuel Lauss
4072a32daf1SManuel Lauss static struct platform_device db1100_spi_dev = {
4082a32daf1SManuel Lauss .name = "spi_gpio",
4092a32daf1SManuel Lauss .id = 0,
4102a32daf1SManuel Lauss .dev = {
4112a32daf1SManuel Lauss .platform_data = &db1100_spictl_pd,
412994bc7faSManuel Lauss .dma_mask = &au1xxx_all_dmamask,
413994bc7faSManuel Lauss .coherent_dma_mask = DMA_BIT_MASK(32),
4142a32daf1SManuel Lauss },
4152a32daf1SManuel Lauss };
4162a32daf1SManuel Lauss
4179b00bc7bSLinus Walleij /*
4189b00bc7bSLinus Walleij * Alchemy GPIO 2 has its base at 200 so the GPIO lines
4199b00bc7bSLinus Walleij * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip.
4209b00bc7bSLinus Walleij */
4219b00bc7bSLinus Walleij static struct gpiod_lookup_table db1100_spi_gpiod_table = {
4229b00bc7bSLinus Walleij .dev_id = "spi_gpio",
4239b00bc7bSLinus Walleij .table = {
4249b00bc7bSLinus Walleij GPIO_LOOKUP("alchemy-gpio2", 9,
4259b00bc7bSLinus Walleij "sck", GPIO_ACTIVE_HIGH),
4269b00bc7bSLinus Walleij GPIO_LOOKUP("alchemy-gpio2", 8,
4279b00bc7bSLinus Walleij "mosi", GPIO_ACTIVE_HIGH),
4289b00bc7bSLinus Walleij GPIO_LOOKUP("alchemy-gpio2", 7,
4299b00bc7bSLinus Walleij "miso", GPIO_ACTIVE_HIGH),
4309b00bc7bSLinus Walleij GPIO_LOOKUP("alchemy-gpio2", 10,
4319b00bc7bSLinus Walleij "cs", GPIO_ACTIVE_HIGH),
4329b00bc7bSLinus Walleij { },
4339b00bc7bSLinus Walleij },
4349b00bc7bSLinus Walleij };
4352a32daf1SManuel Lauss
436f59c811fSManuel Lauss static struct platform_device *db1x00_devs[] = {
437f59c811fSManuel Lauss &db1x00_codec_dev,
438f59c811fSManuel Lauss &alchemy_ac97c_dma_dev,
439f59c811fSManuel Lauss &alchemy_ac97c_dev,
440f59c811fSManuel Lauss &db1x00_audio_dev,
441f59c811fSManuel Lauss };
442f59c811fSManuel Lauss
443f59c811fSManuel Lauss static struct platform_device *db1100_devs[] = {
444f59c811fSManuel Lauss &au1100_lcd_device,
445*ef8f8f04SChristoph Hellwig #ifdef CONFIG_MMC_AU1X
446c9af5144SManuel Lauss &db1100_mmc0_dev,
447c9af5144SManuel Lauss &db1100_mmc1_dev,
448*ef8f8f04SChristoph Hellwig #endif
449f59c811fSManuel Lauss };
450f59c811fSManuel Lauss
db1000_dev_setup(void)451970e268dSManuel Lauss int __init db1000_dev_setup(void)
452f59c811fSManuel Lauss {
453f59c811fSManuel Lauss int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
454851d4f5dSManuel Lauss int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1;
4552a32daf1SManuel Lauss unsigned long pfc;
4566b1889c1SManuel Lauss struct clk *c, *p;
457f59c811fSManuel Lauss
458f59c811fSManuel Lauss if (board == BCSR_WHOAMI_DB1500) {
459f59c811fSManuel Lauss c0 = AU1500_GPIO2_INT;
460f59c811fSManuel Lauss c1 = AU1500_GPIO5_INT;
461e34b6fcfSManuel Lauss d0 = 0; /* GPIO number, NOT irq! */
462e34b6fcfSManuel Lauss d1 = 3; /* GPIO number, NOT irq! */
463f59c811fSManuel Lauss s0 = AU1500_GPIO1_INT;
464f59c811fSManuel Lauss s1 = AU1500_GPIO4_INT;
465f59c811fSManuel Lauss } else if (board == BCSR_WHOAMI_DB1100) {
466f59c811fSManuel Lauss c0 = AU1100_GPIO2_INT;
467f59c811fSManuel Lauss c1 = AU1100_GPIO5_INT;
468e34b6fcfSManuel Lauss d0 = 0; /* GPIO number, NOT irq! */
469e34b6fcfSManuel Lauss d1 = 3; /* GPIO number, NOT irq! */
470f59c811fSManuel Lauss s0 = AU1100_GPIO1_INT;
471f59c811fSManuel Lauss s1 = AU1100_GPIO4_INT;
472c9af5144SManuel Lauss
4734294ad1cSManuel Lauss gpio_request(19, "sd0_cd");
4744294ad1cSManuel Lauss gpio_request(20, "sd1_cd");
475c9af5144SManuel Lauss gpio_direction_input(19); /* sd0 cd# */
476c9af5144SManuel Lauss gpio_direction_input(20); /* sd1 cd# */
4772a32daf1SManuel Lauss
4782a32daf1SManuel Lauss /* spi_gpio on SSI0 pins */
4791d09de7dSManuel Lauss pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
4802a32daf1SManuel Lauss pfc |= (1 << 0); /* SSI0 pins as GPIOs */
4811d09de7dSManuel Lauss alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
4822a32daf1SManuel Lauss
483767d8336SLinus Walleij gpiod_add_lookup_table(&db1100_touch_gpio_table);
4842a32daf1SManuel Lauss spi_register_board_info(db1100_spi_info,
4852a32daf1SManuel Lauss ARRAY_SIZE(db1100_spi_info));
486c9af5144SManuel Lauss
4876b1889c1SManuel Lauss /* link LCD clock to AUXPLL */
4886b1889c1SManuel Lauss p = clk_get(NULL, "auxpll_clk");
4896b1889c1SManuel Lauss c = clk_get(NULL, "lcd_intclk");
4906b1889c1SManuel Lauss if (!IS_ERR(c) && !IS_ERR(p)) {
4916b1889c1SManuel Lauss clk_set_parent(c, p);
4926b1889c1SManuel Lauss clk_set_rate(c, clk_get_rate(p));
4936b1889c1SManuel Lauss }
4946b1889c1SManuel Lauss if (!IS_ERR(c))
4956b1889c1SManuel Lauss clk_put(c);
4966b1889c1SManuel Lauss if (!IS_ERR(p))
4976b1889c1SManuel Lauss clk_put(p);
4986b1889c1SManuel Lauss
499f59c811fSManuel Lauss platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
5009b00bc7bSLinus Walleij gpiod_add_lookup_table(&db1100_spi_gpiod_table);
501851d4f5dSManuel Lauss platform_device_register(&db1100_spi_dev);
502f59c811fSManuel Lauss } else if (board == BCSR_WHOAMI_DB1000) {
503f59c811fSManuel Lauss c0 = AU1000_GPIO2_INT;
504f59c811fSManuel Lauss c1 = AU1000_GPIO5_INT;
505e34b6fcfSManuel Lauss d0 = 0; /* GPIO number, NOT irq! */
506e34b6fcfSManuel Lauss d1 = 3; /* GPIO number, NOT irq! */
507f59c811fSManuel Lauss s0 = AU1000_GPIO1_INT;
508f59c811fSManuel Lauss s1 = AU1000_GPIO4_INT;
509851d4f5dSManuel Lauss } else if ((board == BCSR_WHOAMI_PB1500) ||
510851d4f5dSManuel Lauss (board == BCSR_WHOAMI_PB1500R2)) {
511851d4f5dSManuel Lauss c0 = AU1500_GPIO203_INT;
512e34b6fcfSManuel Lauss d0 = 1; /* GPIO number, NOT irq! */
513851d4f5dSManuel Lauss s0 = AU1500_GPIO202_INT;
514851d4f5dSManuel Lauss twosocks = 0;
515851d4f5dSManuel Lauss flashsize = 64;
516851d4f5dSManuel Lauss /* RTC and daughtercard irqs */
517851d4f5dSManuel Lauss irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
518851d4f5dSManuel Lauss irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
519851d4f5dSManuel Lauss /* EPSON S1D13806 0x1b000000
520851d4f5dSManuel Lauss * SRAM 1MB/2MB 0x1a000000
521851d4f5dSManuel Lauss * DS1693 RTC 0x0c000000
522851d4f5dSManuel Lauss */
523851d4f5dSManuel Lauss } else if (board == BCSR_WHOAMI_PB1100) {
524851d4f5dSManuel Lauss c0 = AU1100_GPIO11_INT;
525e34b6fcfSManuel Lauss d0 = 9; /* GPIO number, NOT irq! */
526851d4f5dSManuel Lauss s0 = AU1100_GPIO10_INT;
527851d4f5dSManuel Lauss twosocks = 0;
528851d4f5dSManuel Lauss flashsize = 64;
529851d4f5dSManuel Lauss /* pendown, rtc, daughtercard irqs */
530851d4f5dSManuel Lauss irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW);
531851d4f5dSManuel Lauss irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
532851d4f5dSManuel Lauss irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
533851d4f5dSManuel Lauss /* EPSON S1D13806 0x1b000000
534851d4f5dSManuel Lauss * SRAM 1MB/2MB 0x1a000000
535851d4f5dSManuel Lauss * DiskOnChip 0x0d000000
536851d4f5dSManuel Lauss * DS1693 RTC 0x0c000000
537851d4f5dSManuel Lauss */
538851d4f5dSManuel Lauss platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
539f59c811fSManuel Lauss } else
540f59c811fSManuel Lauss return 0; /* unknown board, no further dev setup to do */
541f59c811fSManuel Lauss
542f59c811fSManuel Lauss irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
543f59c811fSManuel Lauss irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
544f59c811fSManuel Lauss
545f59c811fSManuel Lauss db1x_register_pcmcia_socket(
546f59c811fSManuel Lauss AU1000_PCMCIA_ATTR_PHYS_ADDR,
547f59c811fSManuel Lauss AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
548f59c811fSManuel Lauss AU1000_PCMCIA_MEM_PHYS_ADDR,
549f59c811fSManuel Lauss AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
550f59c811fSManuel Lauss AU1000_PCMCIA_IO_PHYS_ADDR,
551f59c811fSManuel Lauss AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
552f59c811fSManuel Lauss c0, d0, /*s0*/0, 0, 0);
553f59c811fSManuel Lauss
554851d4f5dSManuel Lauss if (twosocks) {
555851d4f5dSManuel Lauss irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
556851d4f5dSManuel Lauss irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
557851d4f5dSManuel Lauss
558f59c811fSManuel Lauss db1x_register_pcmcia_socket(
559f59c811fSManuel Lauss AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
560f59c811fSManuel Lauss AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
561f59c811fSManuel Lauss AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
562f59c811fSManuel Lauss AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
563f59c811fSManuel Lauss AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
564f59c811fSManuel Lauss AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
565f59c811fSManuel Lauss c1, d1, /*s1*/0, 0, 1);
566851d4f5dSManuel Lauss }
567f59c811fSManuel Lauss
568f59c811fSManuel Lauss platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
569851d4f5dSManuel Lauss db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
570f59c811fSManuel Lauss return 0;
571f59c811fSManuel Lauss }
572