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/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/openbmc/linux/arch/sh/include/mach-se/mach/
H A Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
13 __raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in mrshpc_setup_windows()
15 __raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ in mrshpc_setup_windows()
23 __raw_writew(0x8a84, MRSHPC_MW0CR1); in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
26 __raw_writew(0x0b00, MRSHPC_MW0CR2); in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
29 __raw_writew(0x0300, MRSHPC_MW0CR2); in mrshpc_setup_windows()
32 __raw_writew(0x8a85, MRSHPC_MW1CR1); in mrshpc_setup_windows()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Domap3xxx-clocks.dtsi12 #clock-cells = <0>;
18 #clock-cells = <0>;
21 reg = <0x0d40>;
25 #clock-cells = <0>;
30 reg = <0x1270>;
35 #clock-cells = <0>;
38 reg = <0x0d70>;
43 #clock-cells = <0>;
51 #clock-cells = <0>;
59 #clock-cells = <0>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi12 #clock-cells = <0>;
20 #clock-cells = <0>;
24 reg = <0x0a14>;
28 #clock-cells = <0>;
31 reg = <0x0a14>;
36 #clock-cells = <0>;
39 reg = <0x0a14>;
44 #clock-cells = <0>;
47 reg = <0x0a14>;
48 ti,bit-shift = <0>;
[all …]
/openbmc/u-boot/drivers/pcmcia/
H A Dmarubun_pcmcia.c46 outw( 0x0000 , MRSHPC_MODE ); in pcmcia_on()
48 if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */ in pcmcia_on()
49 if ((inw(MRSHPC_CSR) & 0x0080) == 0){ in pcmcia_on()
50 outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ in pcmcia_on()
52 outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */ in pcmcia_on()
63 outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */ in pcmcia_on()
64 if ((inw(MRSHPC_CSR) & 0x4000) != 0) in pcmcia_on()
65 outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */ in pcmcia_on()
67 outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */ in pcmcia_on()
70 outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */ in pcmcia_on()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dgate.txt33 - #clock-cells : from common clock binding; shall be set to 0
47 #clock-cells = <0>;
50 reg = <0x0a00>;
55 #clock-cells = <0>;
58 reg = <0x0a00>;
63 #clock-cells = <0>;
66 reg = <0x0e00>;
67 ti,bit-shift = <0>;
71 #clock-cells = <0>;
74 reg = <0x059c>;
[all …]
/openbmc/qemu/include/hw/acpi/
H A Dpc-hotplug.h28 #define ICH9_CPU_HOTPLUG_IO_BASE 0x0CD8
29 #define PIIX4_CPU_HOTPLUG_IO_BASE 0xaf00
32 #define ACPI_MEMORY_HOTPLUG_BASE 0x0a00
/openbmc/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c13 #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
14 #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
15 #define SERDES_COMLANE_REGS 0x0a00
16 #define SERDES_WIZ_REGS 0x1fc0
18 #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
19 #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
20 #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
21 #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
22 #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
23 #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dprcm43xx.h15 #define AM43XX_PRM_OCP_SOCKET_INST 0x0000
16 #define AM43XX_PRM_MPU_INST 0x0300
17 #define AM43XX_PRM_GFX_INST 0x0400
18 #define AM43XX_PRM_RTC_INST 0x0500
19 #define AM43XX_PRM_TAMPER_INST 0x0600
20 #define AM43XX_PRM_CEFUSE_INST 0x0700
21 #define AM43XX_PRM_PER_INST 0x0800
22 #define AM43XX_PRM_WKUP_INST 0x2000
23 #define AM43XX_PRM_DEVICE_INST 0x4000
26 #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
[all …]
H A Dprcm_mpu7xx.h24 #define DRA7XX_PRCM_MPU_BASE 0x48243000
30 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
31 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
32 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
33 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
34 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
35 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
38 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
39 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
45 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dprcm_mpu54xx.h24 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
30 #define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
31 #define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
32 #define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
33 #define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
34 #define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
35 #define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
38 #define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
39 #define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
52 #define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
[all …]
H A Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dtegra186_gpio.c66 return 0; in tegra186_gpio_set_out()
82 return 0; in tegra186_gpio_set_val()
95 ret = tegra186_gpio_set_val(dev, offset, value != 0); in tegra186_gpio_direction_output()
122 return tegra186_gpio_set_val(dev, offset, value != 0); in tegra186_gpio_set_value()
143 gpio = args->args[0]; in tegra186_gpio_xlate()
149 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; in tegra186_gpio_xlate()
151 return 0; in tegra186_gpio_xlate()
177 return 0; in tegra186_gpio_bind()
183 for (port = 0; port < ctlr_data->port_count; port++) { in tegra186_gpio_bind()
200 return 0; in tegra186_gpio_bind()
[all …]
/openbmc/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_dev.c13 .qc_idx_mask = GENMASK(8, 0),
14 .qc_addr_offset = 0x400000,
19 .pcie_cfg_expbar_offset = 0x0a00,
20 .pcie_expl_offset = 0xd000,
21 .qc_area_sz = 0x100000,
25 .qc_idx_mask = GENMASK(8, 0),
26 .qc_addr_offset = 0,
32 .qc_idx_mask = GENMASK(7, 0),
33 .qc_addr_offset = 0x80000,
38 .pcie_cfg_expbar_offset = 0x0400,
[all …]
/openbmc/linux/drivers/net/phy/
H A Dmdio-open-alliance.h14 #define MDIO_OATC14_PLCA_IDVER 0xca00 /* PLCA ID and version */
15 #define MDIO_OATC14_PLCA_CTRL0 0xca01 /* PLCA Control register 0 */
16 #define MDIO_OATC14_PLCA_CTRL1 0xca02 /* PLCA Control register 1 */
17 #define MDIO_OATC14_PLCA_STATUS 0xca03 /* PLCA Status register */
18 #define MDIO_OATC14_PLCA_TOTMR 0xca04 /* PLCA TO Timer register */
19 #define MDIO_OATC14_PLCA_BURST 0xca05 /* PLCA BURST mode register */
22 #define MDIO_OATC14_PLCA_IDM 0xff00 /* PLCA MAP ID */
23 #define MDIO_OATC14_PLCA_VER 0x00ff /* PLCA MAP version */
30 #define MDIO_OATC14_PLCA_NCNT 0xff00 /* PLCA node count */
31 #define MDIO_OATC14_PLCA_ID 0x00ff /* PLCA local node ID */
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/openbmc/u-boot/board/st/stm32mp1/
H A Dboard.c18 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) in board_debug_uart_init()
19 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) in board_debug_uart_init()
24 #define GPIOG_BASE 0x50008000 in board_debug_uart_init()
30 writel(0xffbfffff, GPIOG_BASE + 0x00); in board_debug_uart_init()
31 writel(0x00006000, GPIOG_BASE + 0x24); in board_debug_uart_init()
50 return 0; in board_ddr_power_init()
54 if (ret < 0) in board_ddr_power_init()
63 if (ret < 0) in board_ddr_power_init()
71 if (ret < 0) in board_ddr_power_init()
78 if (ret < 0) in board_ddr_power_init()
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dhi556.c23 #define HI556_REG_CHIP_ID 0x0f16
24 #define HI556_CHIP_ID 0x0556
26 #define HI556_REG_MODE_SELECT 0x0a00
27 #define HI556_MODE_STANDBY 0x0000
28 #define HI556_MODE_STREAMING 0x0100
31 #define HI556_REG_FLL 0x0006
32 #define HI556_FLL_30FPS 0x0814
33 #define HI556_FLL_30FPS_MIN 0x0814
34 #define HI556_FLL_MAX 0x7fff
37 #define HI556_REG_LLP 0x0008
[all …]
/openbmc/linux/drivers/clk/bcm/
H A Dclk-bcm281xx.c16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
17 .trig = TRIGGER(0x0e04, 0),
18 .div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
34 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
38 .sel = SELECTOR(0x0a10, 0, 2),
39 .trig = TRIGGER(0x0a40, 4),
43 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
47 .sel = SELECTOR(0x0a04, 0, 2),
48 .div = DIVIDER(0x0a04, 3, 4),
49 .trig = TRIGGER(0x0a40, 0),
[all …]
/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-technisat-usb2.c32 {0x0a0c, KEY_POWER},
33 {0x0a01, KEY_NUMERIC_1},
34 {0x0a02, KEY_NUMERIC_2},
35 {0x0a03, KEY_NUMERIC_3},
36 {0x0a0d, KEY_MUTE},
37 {0x0a04, KEY_NUMERIC_4},
38 {0x0a05, KEY_NUMERIC_5},
39 {0x0a06, KEY_NUMERIC_6},
40 {0x0a38, KEY_VIDEO}, /* EXT */
41 {0x0a07, KEY_NUMERIC_7},
[all …]
/openbmc/openbmc/poky/meta/recipes-core/glibc/ldconfig-native-2.12.1/
H A Dadd-riscv-support.patch33 case 0:
41 #define FLAG_ARM_LIBHF 0x0900
42 #define FLAG_AARCH64_LIB64 0x0a00
43 #define FLAG_ARM_LIBSF 0x0b00
44 +#define FLAG_RISCV_FLOAT_ABI_SOFT 0x0f00
45 +#define FLAG_RISCV_FLOAT_ABI_DOUBLE 0x1000
75 error(0, 0, "%s is a 64-bit ELF for unknown machine %lx\n",
/openbmc/linux/sound/soc/codecs/
H A Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]

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