Searched +full:0 +full:x03d00000 (Results 1 – 14 of 14) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | qcom,sm7150-tlmm.yaml | 74 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$" 122 reg = <0x03500000 0x300000>, 123 <0x03900000 0x300000>, 124 <0x03d00000 0x300000>; 127 gpio-ranges = <&tlmm 0 0 120>;
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H A D | qcom,sc7180-pinctrl.yaml | 71 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$" 123 reg = <0x03500000 0x300000>, 124 <0x03900000 0x300000>, 125 <0x03d00000 0x300000>; 132 gpio-ranges = <&tlmm 0 0 120>;
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H A D | qcom,sc8180x-tlmm.yaml | 74 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$" 114 reg = <0x03100000 0x300000>, 115 <0x03500000 0x700000>, 116 <0x03d00000 0x300000>; 123 gpio-ranges = <&tlmm 0 0 190>;
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H A D | qcom,sm8150-pinctrl.yaml | 72 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$" 124 reg = <0x03100000 0x300000>, 125 <0x03500000 0x300000>, 126 <0x03900000 0x300000>, 127 <0x03d00000 0x300000>; 130 gpio-ranges = <&tlmm 0 0 176>;
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/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/ |
H A D | ns2-xmc.dts | 47 bootargs = "earlycon=uart8250,mmio32,0x66130000"; 52 reg = <0x00000000 0x80000000 0x00000001 0x00000000>; 71 reg = <0x10>; 77 nandcs@0 { 79 reg = <0>; 88 partition@0 { 90 reg = <0x00000000 0x00280000>; /* 2.5MB */ 96 reg = <0x00280000 0x00040000>; /* 0.25MB */ 102 reg = <0x002c0000 0x00040000>; /* 0.25MB */ 108 reg = <0x00300000 0x03d00000>; /* 61MB */ [all …]
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/openbmc/linux/drivers/soc/tegra/cbb/ |
H A D | tegra194-cbb.c | 27 #define ERRLOGGER_0_ID_COREID_0 0x00000000 28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004 29 #define ERRLOGGER_0_FAULTEN_0 0x00000008 30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c 31 #define ERRLOGGER_0_ERRCLR_0 0x00000010 32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014 33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018 34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c 35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020 36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024 [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sm6350.dtsi | 31 #clock-cells = <0>; 39 #clock-cells = <0>; 45 #size-cells = <0>; 47 CPU0: cpu@0 { 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 86 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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H A D | sc8180x.dtsi | 27 #clock-cells = <0>; 33 #clock-cells = <0>; 41 #size-cells = <0>; 43 CPU0: cpu@0 { 46 reg = <0x0 0x0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 57 clocks = <&cpufreq_hw 0>; 75 reg = <0x0 0x100>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 86 clocks = <&cpufreq_hw 0>; [all …]
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H A D | sm8350.dtsi | 36 #clock-cells = <0>; 44 #clock-cells = <0>; 50 #size-cells = <0>; 52 CPU0: cpu@0 { 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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H A D | sc7180.dtsi | 63 #clock-cells = <0>; 69 #clock-cells = <0>; 75 #size-cells = <0>; 77 cpu0: cpu@0 { 80 reg = <0x0 0x0>; 81 clocks = <&cpufreq_hw 0>; 92 qcom,freq-domain = <&cpufreq_hw 0>; 109 reg = <0x0 0x100>; 110 clocks = <&cpufreq_hw 0>; 121 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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H A D | sm8150.dtsi | 30 #clock-cells = <0>; 37 #clock-cells = <0>; 45 #size-cells = <0>; 47 CPU0: cpu@0 { 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; [all …]
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H A D | sc8280xp.dtsi | 32 #clock-cells = <0>; 37 #clock-cells = <0>; 44 #size-cells = <0>; 46 CPU0: cpu@0 { 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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H A D | sc7280.dtsi | 78 #clock-cells = <0>; 84 #clock-cells = <0>; 95 reg = <0x0 0x004cd000 0x0 0x1000>; 99 reg = <0x0 0x80000000 0x0 0x600000>; 104 reg = <0x0 0x80600000 0x0 0x200000>; 109 reg = <0x0 0x80800000 0x0 0x60000>; 114 reg = <0x0 0x80860000 0x0 0x20000>; 120 reg = <0x0 0x80884000 0x0 0x10000>; 125 reg = <0x0 0x808ff000 0x0 0x1000>; 130 reg = <0x0 0x80900000 0x0 0x200000>; [all …]
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H A D | sm8250.dtsi | 81 #clock-cells = <0>; 89 #clock-cells = <0>; 95 #size-cells = <0>; 97 CPU0: cpu@0 { 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 116 cache-size = <0x20000>; 122 cache-size = <0x400000>; [all …]
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