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/openbmc/linux/include/net/
H A Dieee80211_radiotap.h29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/openbmc/u-boot/doc/device-tree-bindings/mailbox/
H A Dnvidia,tegra186-hsp.txt43 reg = <0x0 0x03c00000 0x0 0xa0000>;
/openbmc/linux/arch/mips/lantiq/falcon/
H A Dprom.c25 #define PART_MASK 0x0FFFF000
27 #define REV_MASK 0xF0000000
29 #define SREV_MASK 0x03C00000
31 #define TYPE_MASK 0x3C000000
34 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
35 #define BOOT_RVEC (BOOT_REG_BASE | 0x00)
36 #define BOOT_NVEC (BOOT_REG_BASE | 0x04)
37 #define BOOT_EVEC (BOOT_REG_BASE | 0x08)
61 sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), in ltq_soc_detect()
62 i->rev & 0x7, (i->srev & 0x3) + 1); in ltq_soc_detect()
[all …]
/openbmc/linux/include/uapi/linux/
H A Dkfd_sysfs.h28 #define HSA_CAP_HOT_PLUGGABLE 0x00000001
29 #define HSA_CAP_ATS_PRESENT 0x00000002
30 #define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004
31 #define HSA_CAP_QUEUE_SIZE_POW2 0x00000008
32 #define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010
33 #define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020
34 #define HSA_CAP_VA_LIMIT 0x00000040
35 #define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
36 #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
38 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dnvidia,tegra186-hsp.yaml34 - bits 7..0:
51 - bits 23..0:
63 pattern: "^hsp@[0-9a-f]+$"
89 - pattern: "^shared[0-7]$"
90 - pattern: "^shared[0-7]$"
91 - pattern: "^shared[0-7]$"
92 - pattern: "^shared[0-7]$"
93 - pattern: "^shared[0-7]$"
94 - pattern: "^shared[0-7]$"
95 - pattern: "^shared[0-7]$"
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar956x_initvals.h41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
H A Dar9003_phy.h23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc5121ads.dts21 nand@0 {
23 reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
28 ranges = <0x0 0x0 0xfc000000 0x04000000
29 0x2 0x0 0x82000000 0x00008000>;
31 flash@0,0 {
33 reg = <0 0x0 0x4000000>;
39 protected@0 {
41 reg = <0x00000000 0x00040000>; // first sector is protected
46 reg = <0x00040000 0x03c00000>; // 60M for filesystem
50 reg = <0x03c40000 0x00280000>; // 2.5M for kernel
[all …]
/openbmc/linux/arch/m68k/sun3x/
H A Ddvma.c29 #define IOMMU_ADDR_MASK 0x03ffe000
30 #define IOMMU_CACHE_INHIBIT 0x00000040
31 #define IOMMU_FULL_BLOCK 0x00000020
32 #define IOMMU_MODIFIED 0x00000010
33 #define IOMMU_USED 0x00000008
34 #define IOMMU_WRITE_PROTECT 0x00000004
35 #define IOMMU_DT_MASK 0x00000003
36 #define IOMMU_DT_INVALID 0x00000000
37 #define IOMMU_DT_VALID 0x00000001
38 #define IOMMU_DT_BAD 0x00000002
[all …]
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml147 reg = <0x03c00000 0xa0000>;
155 reg = <0x30000000 0x50000>;
158 ranges = <0x0 0x30000000 0x50000>;
161 reg = <0x4e000 0x1000>;
167 reg = <0x4f000 0x1000>;
191 #size-cells = <0>;
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dts72xx.c70 #define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */
71 #define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */
82 bits = __raw_readb(addr) & ~0x07; in ts72xx_nand_hwcontrol()
83 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ in ts72xx_nand_hwcontrol()
85 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ in ts72xx_nand_hwcontrol()
100 return !!(__raw_readb(addr) & 0x20); in ts72xx_nand_device_ready()
109 .offset = 0,
128 .chip_offset = 0,
139 .start = 0, /* filled in later */
140 .end = 0, /* filled in later */
[all …]
/openbmc/u-boot/include/
H A Dfsl_esdhc.h24 #define SYSCTL 0x0002e02c
25 #define SYSCTL_INITA 0x08000000
26 #define SYSCTL_TIMEOUT_MASK 0x000f0000
27 #define SYSCTL_CLOCK_MASK 0x0000fff0
29 #define SYSCTL_CKEN 0x00000008
30 #define SYSCTL_PEREN 0x00000004
31 #define SYSCTL_HCKEN 0x00000002
32 #define SYSCTL_IPGEN 0x00000001
34 #define SYSCTL_RSTA 0x01000000
35 #define SYSCTL_RSTC 0x02000000
[all …]
H A Dfsl_qe.h20 #define QE_DATAONLY_BASE 0
37 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
38 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
39 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
40 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
50 #define QE_CR_FLG 0x00010000
51 #define QE_RESET 0x80000000
52 #define QE_INIT_TX_RX 0x00000000
53 #define QE_INIT_RX 0x00000001
54 #define QE_INIT_TX 0x00000002
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra186.dtsi19 <0x0 0x2200000 0x0 0x10000>,
20 <0x0 0x2210000 0x0 0x10000>;
36 reg = <0x0 0x02490000 0x0 0x10000>;
56 reg = <0x0 0x03100000 0x0 0x10000>;
63 reg = <0x0 0x3160000 0x0 0x100>;
66 #size-cells = <0>;
76 reg = <0x0 0x3180000 0x0 0x100>;
79 #size-cells = <0>;
89 reg = <0x0 0x3190000 0x0 0x100>;
92 #size-cells = <0>;
[all …]
H A Dsun9i-a80.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
69 reg = <0x0>;
78 reg = <0x1>;
87 reg = <0x2>;
96 reg = <0x3>;
105 reg = <0x100>;
114 reg = <0x101>;
123 reg = <0x102>;
132 reg = <0x103>;
[all …]
/openbmc/linux/arch/arm/net/
H A Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dspeedstep-lib.c27 #define relaxed_check 0
40 [27, 25:22] (in MSR 0x2a) */ in pentium3_get_frequency()
42 { 30, 0x01 }, in pentium3_get_frequency()
43 { 35, 0x05 }, in pentium3_get_frequency()
44 { 40, 0x02 }, in pentium3_get_frequency()
45 { 45, 0x06 }, in pentium3_get_frequency()
46 { 50, 0x00 }, in pentium3_get_frequency()
47 { 55, 0x04 }, in pentium3_get_frequency()
48 { 60, 0x0b }, in pentium3_get_frequency()
49 { 65, 0x0f }, in pentium3_get_frequency()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-tcon.yaml19 const: 0
122 port@0:
134 "^endpoint(@[0-9])$":
154 - port@0
382 reg = <0x01c0c000 0x1000>;
393 #clock-cells = <0>;
398 #size-cells = <0>;
400 port@0 {
402 #size-cells = <0>;
403 reg = <0>;
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dtargaddrs.h25 #define QCA988X_HOST_INTEREST_ADDRESS 0x00400800
26 #define HOST_INTEREST_MAX_SIZE 0x200
39 u32 hi_app_host_interest; /* 0x00 */
42 u32 hi_failure_state; /* 0x04 */
45 u32 hi_dbglog_hdr; /* 0x08 */
47 u32 hi_unused0c; /* 0x0c */
53 u32 hi_option_flag; /* 0x10 */
59 u32 hi_serial_enable; /* 0x14 */
62 u32 hi_dset_list_head; /* 0x18 */
65 u32 hi_app_start; /* 0x1c */
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dcg14.c58 #define CG14_MCR_INTENABLE_MASK 0x80
60 #define CG14_MCR_VIDENABLE_MASK 0x40
62 #define CG14_MCR_PIXMODE_MASK 0x30
64 #define CG14_MCR_TMR_MASK 0x0c
66 #define CG14_MCR_TMENABLE_MASK 0x02
67 #define CG14_MCR_RESET_SHIFT 0
68 #define CG14_MCR_RESET_MASK 0x01
70 #define CG14_REV_REVISION_MASK 0xf0
71 #define CG14_REV_IMPL_SHIFT 0
72 #define CG14_REV_IMPL_MASK 0x0f
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dkvm.c29 #define KVM_INST_LWZ 0x80000000
30 #define KVM_INST_STW 0x90000000
31 #define KVM_INST_LD 0xe8000000
32 #define KVM_INST_STD 0xf8000000
33 #define KVM_INST_NOP 0x60000000
34 #define KVM_INST_B 0x48000000
35 #define KVM_INST_B_MASK 0x03ffffff
36 #define KVM_INST_B_MAX 0x01ffffff
37 #define KVM_INST_LI 0x38000000
39 #define KVM_MASK_RT 0x03e00000
[all …]
/openbmc/linux/include/soc/fsl/qe/
H A Dqe.h32 QE_CLK_NONE = 0,
131 return 0; in cpm_muram_dma()
227 return 0; in qe_alive_during_sleep()
271 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
284 __be32 traps[16]; /* Trap addresses, 0 == ignore */
328 #define BD_STATUS_MASK 0xffff0000
329 #define BD_LENGTH_MASK 0x0000ffff
337 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
338 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
339 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Ds626.h36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
39 #define S626_EOPL 0x80 /* End of ADC poll list marker. */
40 #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */
41 #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */
44 #define S626_ERR_ILLEGAL_PARM 0x00010000 /*
48 #define S626_ERR_I2C 0x00020000 /* I2C error. */
49 #define S626_ERR_COUNTERSETUP 0x00200000 /*
53 #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */
74 #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dphy.c23 } while (0)
33 return 0; in _rtl8821ae_phy_calculate_bit_shift()
60 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3); in rtl8812ae_fixspur()
61 /* 0x8AC[11:10] = 2'b11*/ in rtl8812ae_fixspur()
63 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2); in rtl8812ae_fixspur()
64 /* 0x8AC[11:10] = 2'b10*/ in rtl8812ae_fixspur()
71 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3); in rtl8812ae_fixspur()
72 /*0x8AC[9:8] = 2'b11*/ in rtl8812ae_fixspur()
74 /* 0x8C4[30] = 1*/ in rtl8812ae_fixspur()
78 /*0x8C4[30] = 1*/ in rtl8812ae_fixspur()
[all …]

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