14f19048fSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2bb0a56ecSDave Jones /*
3bb0a56ecSDave Jones * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4bb0a56ecSDave Jones *
5bb0a56ecSDave Jones * Library for common functions for Intel SpeedStep v.1 and v.2 support
6bb0a56ecSDave Jones *
7bb0a56ecSDave Jones * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
8bb0a56ecSDave Jones */
9bb0a56ecSDave Jones
101c5864e2SJoe Perches #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
111c5864e2SJoe Perches
12bb0a56ecSDave Jones #include <linux/kernel.h>
13bb0a56ecSDave Jones #include <linux/module.h>
14bb0a56ecSDave Jones #include <linux/moduleparam.h>
15bb0a56ecSDave Jones #include <linux/init.h>
16bb0a56ecSDave Jones #include <linux/cpufreq.h>
17bb0a56ecSDave Jones
18bb0a56ecSDave Jones #include <asm/msr.h>
19bb0a56ecSDave Jones #include <asm/tsc.h>
20bb0a56ecSDave Jones #include "speedstep-lib.h"
21bb0a56ecSDave Jones
22bb0a56ecSDave Jones #define PFX "speedstep-lib: "
23bb0a56ecSDave Jones
24bb0a56ecSDave Jones #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
25bb0a56ecSDave Jones static int relaxed_check;
26bb0a56ecSDave Jones #else
27bb0a56ecSDave Jones #define relaxed_check 0
28bb0a56ecSDave Jones #endif
29bb0a56ecSDave Jones
30bb0a56ecSDave Jones /*********************************************************************
31bb0a56ecSDave Jones * GET PROCESSOR CORE SPEED IN KHZ *
32bb0a56ecSDave Jones *********************************************************************/
33bb0a56ecSDave Jones
pentium3_get_frequency(enum speedstep_processor processor)34bb0a56ecSDave Jones static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
35bb0a56ecSDave Jones {
36bb0a56ecSDave Jones /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
37843791bbSColin Ian King static const struct {
38bb0a56ecSDave Jones unsigned int ratio; /* Frequency Multiplier (x10) */
39bb0a56ecSDave Jones u8 bitmap; /* power on configuration bits
40bb0a56ecSDave Jones [27, 25:22] (in MSR 0x2a) */
41bb0a56ecSDave Jones } msr_decode_mult[] = {
42bb0a56ecSDave Jones { 30, 0x01 },
43bb0a56ecSDave Jones { 35, 0x05 },
44bb0a56ecSDave Jones { 40, 0x02 },
45bb0a56ecSDave Jones { 45, 0x06 },
46bb0a56ecSDave Jones { 50, 0x00 },
47bb0a56ecSDave Jones { 55, 0x04 },
48bb0a56ecSDave Jones { 60, 0x0b },
49bb0a56ecSDave Jones { 65, 0x0f },
50bb0a56ecSDave Jones { 70, 0x09 },
51bb0a56ecSDave Jones { 75, 0x0d },
52bb0a56ecSDave Jones { 80, 0x0a },
53bb0a56ecSDave Jones { 85, 0x26 },
54bb0a56ecSDave Jones { 90, 0x20 },
55bb0a56ecSDave Jones { 100, 0x2b },
56bb0a56ecSDave Jones { 0, 0xff } /* error or unknown value */
57bb0a56ecSDave Jones };
58bb0a56ecSDave Jones
59bb0a56ecSDave Jones /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
60843791bbSColin Ian King static const struct {
61bb0a56ecSDave Jones unsigned int value; /* Front Side Bus speed in MHz */
62bb0a56ecSDave Jones u8 bitmap; /* power on configuration bits [18: 19]
63bb0a56ecSDave Jones (in MSR 0x2a) */
64bb0a56ecSDave Jones } msr_decode_fsb[] = {
65bb0a56ecSDave Jones { 66, 0x0 },
66bb0a56ecSDave Jones { 100, 0x2 },
67bb0a56ecSDave Jones { 133, 0x1 },
68bb0a56ecSDave Jones { 0, 0xff}
69bb0a56ecSDave Jones };
70bb0a56ecSDave Jones
71bb0a56ecSDave Jones u32 msr_lo, msr_tmp;
72bb0a56ecSDave Jones int i = 0, j = 0;
73bb0a56ecSDave Jones
74bb0a56ecSDave Jones /* read MSR 0x2a - we only need the low 32 bits */
75bb0a56ecSDave Jones rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
76bb0a56ecSDave Jones pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
77bb0a56ecSDave Jones msr_tmp = msr_lo;
78bb0a56ecSDave Jones
79bb0a56ecSDave Jones /* decode the FSB */
80bb0a56ecSDave Jones msr_tmp &= 0x00c0000;
81bb0a56ecSDave Jones msr_tmp >>= 18;
82bb0a56ecSDave Jones while (msr_tmp != msr_decode_fsb[i].bitmap) {
83bb0a56ecSDave Jones if (msr_decode_fsb[i].bitmap == 0xff)
84bb0a56ecSDave Jones return 0;
85bb0a56ecSDave Jones i++;
86bb0a56ecSDave Jones }
87bb0a56ecSDave Jones
88bb0a56ecSDave Jones /* decode the multiplier */
89bb0a56ecSDave Jones if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
90bb0a56ecSDave Jones pr_debug("workaround for early PIIIs\n");
91bb0a56ecSDave Jones msr_lo &= 0x03c00000;
92bb0a56ecSDave Jones } else
93bb0a56ecSDave Jones msr_lo &= 0x0bc00000;
94bb0a56ecSDave Jones msr_lo >>= 22;
95bb0a56ecSDave Jones while (msr_lo != msr_decode_mult[j].bitmap) {
96bb0a56ecSDave Jones if (msr_decode_mult[j].bitmap == 0xff)
97bb0a56ecSDave Jones return 0;
98bb0a56ecSDave Jones j++;
99bb0a56ecSDave Jones }
100bb0a56ecSDave Jones
101bb0a56ecSDave Jones pr_debug("speed is %u\n",
102bb0a56ecSDave Jones (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
103bb0a56ecSDave Jones
104bb0a56ecSDave Jones return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
105bb0a56ecSDave Jones }
106bb0a56ecSDave Jones
107bb0a56ecSDave Jones
pentiumM_get_frequency(void)108bb0a56ecSDave Jones static unsigned int pentiumM_get_frequency(void)
109bb0a56ecSDave Jones {
110bb0a56ecSDave Jones u32 msr_lo, msr_tmp;
111bb0a56ecSDave Jones
112bb0a56ecSDave Jones rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
113bb0a56ecSDave Jones pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
114bb0a56ecSDave Jones
115bb0a56ecSDave Jones /* see table B-2 of 24547212.pdf */
116bb0a56ecSDave Jones if (msr_lo & 0x00040000) {
117bb0a56ecSDave Jones printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
118bb0a56ecSDave Jones msr_lo, msr_tmp);
119bb0a56ecSDave Jones return 0;
120bb0a56ecSDave Jones }
121bb0a56ecSDave Jones
122bb0a56ecSDave Jones msr_tmp = (msr_lo >> 22) & 0x1f;
123bb0a56ecSDave Jones pr_debug("bits 22-26 are 0x%x, speed is %u\n",
124bb0a56ecSDave Jones msr_tmp, (msr_tmp * 100 * 1000));
125bb0a56ecSDave Jones
126bb0a56ecSDave Jones return msr_tmp * 100 * 1000;
127bb0a56ecSDave Jones }
128bb0a56ecSDave Jones
pentium_core_get_frequency(void)129bb0a56ecSDave Jones static unsigned int pentium_core_get_frequency(void)
130bb0a56ecSDave Jones {
131bb0a56ecSDave Jones u32 fsb = 0;
132bb0a56ecSDave Jones u32 msr_lo, msr_tmp;
133bb0a56ecSDave Jones int ret;
134bb0a56ecSDave Jones
135bb0a56ecSDave Jones rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
136bb0a56ecSDave Jones /* see table B-2 of 25366920.pdf */
137bb0a56ecSDave Jones switch (msr_lo & 0x07) {
138bb0a56ecSDave Jones case 5:
139bb0a56ecSDave Jones fsb = 100000;
140bb0a56ecSDave Jones break;
141bb0a56ecSDave Jones case 1:
142bb0a56ecSDave Jones fsb = 133333;
143bb0a56ecSDave Jones break;
144bb0a56ecSDave Jones case 3:
145bb0a56ecSDave Jones fsb = 166667;
146bb0a56ecSDave Jones break;
147bb0a56ecSDave Jones case 2:
148bb0a56ecSDave Jones fsb = 200000;
149bb0a56ecSDave Jones break;
150bb0a56ecSDave Jones case 0:
151bb0a56ecSDave Jones fsb = 266667;
152bb0a56ecSDave Jones break;
153bb0a56ecSDave Jones case 4:
154bb0a56ecSDave Jones fsb = 333333;
155bb0a56ecSDave Jones break;
156bb0a56ecSDave Jones default:
157b49c22a6SJoe Perches pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
158bb0a56ecSDave Jones }
159bb0a56ecSDave Jones
160bb0a56ecSDave Jones rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
161bb0a56ecSDave Jones pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
162bb0a56ecSDave Jones msr_lo, msr_tmp);
163bb0a56ecSDave Jones
164bb0a56ecSDave Jones msr_tmp = (msr_lo >> 22) & 0x1f;
165bb0a56ecSDave Jones pr_debug("bits 22-26 are 0x%x, speed is %u\n",
166bb0a56ecSDave Jones msr_tmp, (msr_tmp * fsb));
167bb0a56ecSDave Jones
168bb0a56ecSDave Jones ret = (msr_tmp * fsb);
169bb0a56ecSDave Jones return ret;
170bb0a56ecSDave Jones }
171bb0a56ecSDave Jones
172bb0a56ecSDave Jones
pentium4_get_frequency(void)173bb0a56ecSDave Jones static unsigned int pentium4_get_frequency(void)
174bb0a56ecSDave Jones {
175bb0a56ecSDave Jones struct cpuinfo_x86 *c = &boot_cpu_data;
176bb0a56ecSDave Jones u32 msr_lo, msr_hi, mult;
177bb0a56ecSDave Jones unsigned int fsb = 0;
178bb0a56ecSDave Jones unsigned int ret;
179bb0a56ecSDave Jones u8 fsb_code;
180bb0a56ecSDave Jones
181bb0a56ecSDave Jones /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
182bb0a56ecSDave Jones * to System Bus Frequency Ratio Field in the Processor Frequency
183bb0a56ecSDave Jones * Configuration Register of the MSR. Therefore the current
184bb0a56ecSDave Jones * frequency cannot be calculated and has to be measured.
185bb0a56ecSDave Jones */
186bb0a56ecSDave Jones if (c->x86_model < 2)
187bb0a56ecSDave Jones return cpu_khz;
188bb0a56ecSDave Jones
189bb0a56ecSDave Jones rdmsr(0x2c, msr_lo, msr_hi);
190bb0a56ecSDave Jones
191bb0a56ecSDave Jones pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
192bb0a56ecSDave Jones
193bb0a56ecSDave Jones /* decode the FSB: see IA-32 Intel (C) Architecture Software
194bb0a56ecSDave Jones * Developer's Manual, Volume 3: System Prgramming Guide,
195bb0a56ecSDave Jones * revision #12 in Table B-1: MSRs in the Pentium 4 and
196bb0a56ecSDave Jones * Intel Xeon Processors, on page B-4 and B-5.
197bb0a56ecSDave Jones */
198bb0a56ecSDave Jones fsb_code = (msr_lo >> 16) & 0x7;
199bb0a56ecSDave Jones switch (fsb_code) {
200bb0a56ecSDave Jones case 0:
201bb0a56ecSDave Jones fsb = 100 * 1000;
202bb0a56ecSDave Jones break;
203bb0a56ecSDave Jones case 1:
204bb0a56ecSDave Jones fsb = 13333 * 10;
205bb0a56ecSDave Jones break;
206bb0a56ecSDave Jones case 2:
207bb0a56ecSDave Jones fsb = 200 * 1000;
208bb0a56ecSDave Jones break;
209bb0a56ecSDave Jones }
210bb0a56ecSDave Jones
211bb0a56ecSDave Jones if (!fsb)
212bb0a56ecSDave Jones printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
213bb0a56ecSDave Jones "Please send an e-mail to <linux@brodo.de>\n");
214bb0a56ecSDave Jones
215bb0a56ecSDave Jones /* Multiplier. */
216bb0a56ecSDave Jones mult = msr_lo >> 24;
217bb0a56ecSDave Jones
218bb0a56ecSDave Jones pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
219bb0a56ecSDave Jones fsb, mult, (fsb * mult));
220bb0a56ecSDave Jones
221bb0a56ecSDave Jones ret = (fsb * mult);
222bb0a56ecSDave Jones return ret;
223bb0a56ecSDave Jones }
224bb0a56ecSDave Jones
225bb0a56ecSDave Jones
226bb0a56ecSDave Jones /* Warning: may get called from smp_call_function_single. */
speedstep_get_frequency(enum speedstep_processor processor)227bb0a56ecSDave Jones unsigned int speedstep_get_frequency(enum speedstep_processor processor)
228bb0a56ecSDave Jones {
229bb0a56ecSDave Jones switch (processor) {
230bb0a56ecSDave Jones case SPEEDSTEP_CPU_PCORE:
231bb0a56ecSDave Jones return pentium_core_get_frequency();
232bb0a56ecSDave Jones case SPEEDSTEP_CPU_PM:
233bb0a56ecSDave Jones return pentiumM_get_frequency();
234bb0a56ecSDave Jones case SPEEDSTEP_CPU_P4D:
235bb0a56ecSDave Jones case SPEEDSTEP_CPU_P4M:
236bb0a56ecSDave Jones return pentium4_get_frequency();
237bb0a56ecSDave Jones case SPEEDSTEP_CPU_PIII_T:
238bb0a56ecSDave Jones case SPEEDSTEP_CPU_PIII_C:
239bb0a56ecSDave Jones case SPEEDSTEP_CPU_PIII_C_EARLY:
240bb0a56ecSDave Jones return pentium3_get_frequency(processor);
241bb0a56ecSDave Jones default:
242bb0a56ecSDave Jones return 0;
24300d43947STom Rix }
244bb0a56ecSDave Jones return 0;
245bb0a56ecSDave Jones }
246bb0a56ecSDave Jones EXPORT_SYMBOL_GPL(speedstep_get_frequency);
247bb0a56ecSDave Jones
248bb0a56ecSDave Jones
249bb0a56ecSDave Jones /*********************************************************************
250bb0a56ecSDave Jones * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
251bb0a56ecSDave Jones *********************************************************************/
252bb0a56ecSDave Jones
253fa8031aeSAndi Kleen /* Keep in sync with the x86_cpu_id tables in the different modules */
speedstep_detect_processor(void)254df21443fSLuc Van Oostenryck enum speedstep_processor speedstep_detect_processor(void)
255bb0a56ecSDave Jones {
256bb0a56ecSDave Jones struct cpuinfo_x86 *c = &cpu_data(0);
257bb0a56ecSDave Jones u32 ebx, msr_lo, msr_hi;
258bb0a56ecSDave Jones
259bb0a56ecSDave Jones pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
260bb0a56ecSDave Jones
261bb0a56ecSDave Jones if ((c->x86_vendor != X86_VENDOR_INTEL) ||
262bb0a56ecSDave Jones ((c->x86 != 6) && (c->x86 != 0xF)))
263bb0a56ecSDave Jones return 0;
264bb0a56ecSDave Jones
265bb0a56ecSDave Jones if (c->x86 == 0xF) {
266bb0a56ecSDave Jones /* Intel Mobile Pentium 4-M
267bb0a56ecSDave Jones * or Intel Mobile Pentium 4 with 533 MHz FSB */
268bb0a56ecSDave Jones if (c->x86_model != 2)
269bb0a56ecSDave Jones return 0;
270bb0a56ecSDave Jones
271bb0a56ecSDave Jones ebx = cpuid_ebx(0x00000001);
272bb0a56ecSDave Jones ebx &= 0x000000FF;
273bb0a56ecSDave Jones
274b399151cSJia Zhang pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping);
275bb0a56ecSDave Jones
276b399151cSJia Zhang switch (c->x86_stepping) {
277bb0a56ecSDave Jones case 4:
278bb0a56ecSDave Jones /*
279bb0a56ecSDave Jones * B-stepping [M-P4-M]
280bb0a56ecSDave Jones * sample has ebx = 0x0f, production has 0x0e.
281bb0a56ecSDave Jones */
282bb0a56ecSDave Jones if ((ebx == 0x0e) || (ebx == 0x0f))
283bb0a56ecSDave Jones return SPEEDSTEP_CPU_P4M;
284bb0a56ecSDave Jones break;
285bb0a56ecSDave Jones case 7:
286bb0a56ecSDave Jones /*
287bb0a56ecSDave Jones * C-stepping [M-P4-M]
288bb0a56ecSDave Jones * needs to have ebx=0x0e, else it's a celeron:
289bb0a56ecSDave Jones * cf. 25130917.pdf / page 7, footnote 5 even
290bb0a56ecSDave Jones * though 25072120.pdf / page 7 doesn't say
291bb0a56ecSDave Jones * samples are only of B-stepping...
292bb0a56ecSDave Jones */
293bb0a56ecSDave Jones if (ebx == 0x0e)
294bb0a56ecSDave Jones return SPEEDSTEP_CPU_P4M;
295bb0a56ecSDave Jones break;
296bb0a56ecSDave Jones case 9:
297bb0a56ecSDave Jones /*
298bb0a56ecSDave Jones * D-stepping [M-P4-M or M-P4/533]
299bb0a56ecSDave Jones *
300bb0a56ecSDave Jones * this is totally strange: CPUID 0x0F29 is
301bb0a56ecSDave Jones * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
302bb0a56ecSDave Jones * The latter need to be sorted out as they don't
303bb0a56ecSDave Jones * support speedstep.
304bb0a56ecSDave Jones * Celerons with CPUID 0x0F29 may have either
305bb0a56ecSDave Jones * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
306bb0a56ecSDave Jones * specific.
307bb0a56ecSDave Jones * M-P4-Ms may have either ebx=0xe or 0xf [see above]
308bb0a56ecSDave Jones * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
309bb0a56ecSDave Jones * also, M-P4M HTs have ebx=0x8, too
310bb0a56ecSDave Jones * For now, they are distinguished by the model_id
311bb0a56ecSDave Jones * string
312bb0a56ecSDave Jones */
313bb0a56ecSDave Jones if ((ebx == 0x0e) ||
314bb0a56ecSDave Jones (strstr(c->x86_model_id,
315bb0a56ecSDave Jones "Mobile Intel(R) Pentium(R) 4") != NULL))
316bb0a56ecSDave Jones return SPEEDSTEP_CPU_P4M;
317bb0a56ecSDave Jones break;
318bb0a56ecSDave Jones default:
319bb0a56ecSDave Jones break;
320bb0a56ecSDave Jones }
321bb0a56ecSDave Jones return 0;
322bb0a56ecSDave Jones }
323bb0a56ecSDave Jones
324bb0a56ecSDave Jones switch (c->x86_model) {
325bb0a56ecSDave Jones case 0x0B: /* Intel PIII [Tualatin] */
326bb0a56ecSDave Jones /* cpuid_ebx(1) is 0x04 for desktop PIII,
327bb0a56ecSDave Jones * 0x06 for mobile PIII-M */
328bb0a56ecSDave Jones ebx = cpuid_ebx(0x00000001);
329bb0a56ecSDave Jones pr_debug("ebx is %x\n", ebx);
330bb0a56ecSDave Jones
331bb0a56ecSDave Jones ebx &= 0x000000FF;
332bb0a56ecSDave Jones
333bb0a56ecSDave Jones if (ebx != 0x06)
334bb0a56ecSDave Jones return 0;
335bb0a56ecSDave Jones
336bb0a56ecSDave Jones /* So far all PIII-M processors support SpeedStep. See
337bb0a56ecSDave Jones * Intel's 24540640.pdf of June 2003
338bb0a56ecSDave Jones */
339bb0a56ecSDave Jones return SPEEDSTEP_CPU_PIII_T;
340bb0a56ecSDave Jones
341bb0a56ecSDave Jones case 0x08: /* Intel PIII [Coppermine] */
342bb0a56ecSDave Jones
343bb0a56ecSDave Jones /* all mobile PIII Coppermines have FSB 100 MHz
344bb0a56ecSDave Jones * ==> sort out a few desktop PIIIs. */
345bb0a56ecSDave Jones rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
346bb0a56ecSDave Jones pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
347bb0a56ecSDave Jones msr_lo, msr_hi);
348bb0a56ecSDave Jones msr_lo &= 0x00c0000;
349bb0a56ecSDave Jones if (msr_lo != 0x0080000)
350bb0a56ecSDave Jones return 0;
351bb0a56ecSDave Jones
352bb0a56ecSDave Jones /*
353bb0a56ecSDave Jones * If the processor is a mobile version,
354bb0a56ecSDave Jones * platform ID has bit 50 set
355bb0a56ecSDave Jones * it has SpeedStep technology if either
356bb0a56ecSDave Jones * bit 56 or 57 is set
357bb0a56ecSDave Jones */
358bb0a56ecSDave Jones rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
359bb0a56ecSDave Jones pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
360bb0a56ecSDave Jones msr_lo, msr_hi);
361bb0a56ecSDave Jones if ((msr_hi & (1<<18)) &&
362bb0a56ecSDave Jones (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
363b399151cSJia Zhang if (c->x86_stepping == 0x01) {
364bb0a56ecSDave Jones pr_debug("early PIII version\n");
365bb0a56ecSDave Jones return SPEEDSTEP_CPU_PIII_C_EARLY;
366bb0a56ecSDave Jones } else
367bb0a56ecSDave Jones return SPEEDSTEP_CPU_PIII_C;
368bb0a56ecSDave Jones }
369df561f66SGustavo A. R. Silva fallthrough;
370bb0a56ecSDave Jones default:
371bb0a56ecSDave Jones return 0;
372bb0a56ecSDave Jones }
373bb0a56ecSDave Jones }
374bb0a56ecSDave Jones EXPORT_SYMBOL_GPL(speedstep_detect_processor);
375bb0a56ecSDave Jones
376bb0a56ecSDave Jones
377bb0a56ecSDave Jones /*********************************************************************
378bb0a56ecSDave Jones * DETECT SPEEDSTEP SPEEDS *
379bb0a56ecSDave Jones *********************************************************************/
380bb0a56ecSDave Jones
speedstep_get_freqs(enum speedstep_processor processor,unsigned int * low_speed,unsigned int * high_speed,unsigned int * transition_latency,void (* set_state)(unsigned int state))381bb0a56ecSDave Jones unsigned int speedstep_get_freqs(enum speedstep_processor processor,
382bb0a56ecSDave Jones unsigned int *low_speed,
383bb0a56ecSDave Jones unsigned int *high_speed,
384bb0a56ecSDave Jones unsigned int *transition_latency,
385bb0a56ecSDave Jones void (*set_state) (unsigned int state))
386bb0a56ecSDave Jones {
387bb0a56ecSDave Jones unsigned int prev_speed;
388bb0a56ecSDave Jones unsigned int ret = 0;
389bb0a56ecSDave Jones unsigned long flags;
39072e624deSAbhilash Jindal ktime_t tv1, tv2;
391bb0a56ecSDave Jones
392bb0a56ecSDave Jones if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
393bb0a56ecSDave Jones return -EINVAL;
394bb0a56ecSDave Jones
395bb0a56ecSDave Jones pr_debug("trying to determine both speeds\n");
396bb0a56ecSDave Jones
397bb0a56ecSDave Jones /* get current speed */
398bb0a56ecSDave Jones prev_speed = speedstep_get_frequency(processor);
399bb0a56ecSDave Jones if (!prev_speed)
400bb0a56ecSDave Jones return -EIO;
401bb0a56ecSDave Jones
402bb0a56ecSDave Jones pr_debug("previous speed is %u\n", prev_speed);
403bb0a56ecSDave Jones
404d4d4eda2SMikulas Patocka preempt_disable();
405bb0a56ecSDave Jones local_irq_save(flags);
406bb0a56ecSDave Jones
407bb0a56ecSDave Jones /* switch to low state */
408bb0a56ecSDave Jones set_state(SPEEDSTEP_LOW);
409bb0a56ecSDave Jones *low_speed = speedstep_get_frequency(processor);
410bb0a56ecSDave Jones if (!*low_speed) {
411bb0a56ecSDave Jones ret = -EIO;
412bb0a56ecSDave Jones goto out;
413bb0a56ecSDave Jones }
414bb0a56ecSDave Jones
415bb0a56ecSDave Jones pr_debug("low speed is %u\n", *low_speed);
416bb0a56ecSDave Jones
417bb0a56ecSDave Jones /* start latency measurement */
418bb0a56ecSDave Jones if (transition_latency)
41972e624deSAbhilash Jindal tv1 = ktime_get();
420bb0a56ecSDave Jones
421bb0a56ecSDave Jones /* switch to high state */
422bb0a56ecSDave Jones set_state(SPEEDSTEP_HIGH);
423bb0a56ecSDave Jones
424bb0a56ecSDave Jones /* end latency measurement */
425bb0a56ecSDave Jones if (transition_latency)
42672e624deSAbhilash Jindal tv2 = ktime_get();
427bb0a56ecSDave Jones
428bb0a56ecSDave Jones *high_speed = speedstep_get_frequency(processor);
429bb0a56ecSDave Jones if (!*high_speed) {
430bb0a56ecSDave Jones ret = -EIO;
431bb0a56ecSDave Jones goto out;
432bb0a56ecSDave Jones }
433bb0a56ecSDave Jones
434bb0a56ecSDave Jones pr_debug("high speed is %u\n", *high_speed);
435bb0a56ecSDave Jones
436bb0a56ecSDave Jones if (*low_speed == *high_speed) {
437bb0a56ecSDave Jones ret = -ENODEV;
438bb0a56ecSDave Jones goto out;
439bb0a56ecSDave Jones }
440bb0a56ecSDave Jones
441bb0a56ecSDave Jones /* switch to previous state, if necessary */
442bb0a56ecSDave Jones if (*high_speed != prev_speed)
443bb0a56ecSDave Jones set_state(SPEEDSTEP_LOW);
444bb0a56ecSDave Jones
445bb0a56ecSDave Jones if (transition_latency) {
44672e624deSAbhilash Jindal *transition_latency = ktime_to_us(ktime_sub(tv2, tv1));
447bb0a56ecSDave Jones pr_debug("transition latency is %u uSec\n", *transition_latency);
448bb0a56ecSDave Jones
449bb0a56ecSDave Jones /* convert uSec to nSec and add 20% for safety reasons */
450bb0a56ecSDave Jones *transition_latency *= 1200;
451bb0a56ecSDave Jones
452bb0a56ecSDave Jones /* check if the latency measurement is too high or too low
453bb0a56ecSDave Jones * and set it to a safe value (500uSec) in that case
454bb0a56ecSDave Jones */
455bb0a56ecSDave Jones if (*transition_latency > 10000000 ||
456bb0a56ecSDave Jones *transition_latency < 50000) {
4571c5864e2SJoe Perches pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n",
458bb0a56ecSDave Jones *transition_latency, 500000);
459bb0a56ecSDave Jones *transition_latency = 500000;
460bb0a56ecSDave Jones }
461bb0a56ecSDave Jones }
462bb0a56ecSDave Jones
463bb0a56ecSDave Jones out:
464bb0a56ecSDave Jones local_irq_restore(flags);
465d4d4eda2SMikulas Patocka preempt_enable();
466d4d4eda2SMikulas Patocka
467bb0a56ecSDave Jones return ret;
468bb0a56ecSDave Jones }
469bb0a56ecSDave Jones EXPORT_SYMBOL_GPL(speedstep_get_freqs);
470bb0a56ecSDave Jones
471bb0a56ecSDave Jones #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
472bb0a56ecSDave Jones module_param(relaxed_check, int, 0444);
473bb0a56ecSDave Jones MODULE_PARM_DESC(relaxed_check,
474bb0a56ecSDave Jones "Don't do all checks for speedstep capability.");
475bb0a56ecSDave Jones #endif
476bb0a56ecSDave Jones
477bb0a56ecSDave Jones MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
478bb0a56ecSDave Jones MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
479bb0a56ecSDave Jones MODULE_LICENSE("GPL");
480