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/openbmc/linux/arch/arm64/crypto/
H A Dpoly1305-armv8.pl34 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
44 my ($ctx,$inp,$len,$padbit) = map("x$_",(0..3));
78 mov $s1,#0xfffffffc0fffffff
79 movk $s1,#0x0fff,lsl#48
84 and $r0,$r0,$s1 // &=0ffffffc0fffffff
86 and $r1,$r1,$s1 // &=0ffffffc0ffffffc
145 cmp x17,#0 // is_base2_26?
233 cmp $r0,#0 // is_base2_26?
262 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("v$_.4s",(0..8));
313 and x12,$h0,#0x03ffffff // base 2^64 -> base 2^26
[all …]
/openbmc/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
10 EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220),
11 EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000),
12 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010),
13 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001),
14 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000),
15 EMIT_MASKPOLL(0xf800010c, 0x00000001),
16 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000),
17 EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200),
18 EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220),
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ralink/
H A Dmt7621.h12 #define MT7621_PALMBUS_BASE 0x1C000000
13 #define MT7621_PALMBUS_SIZE 0x03FFFFFF
15 #define MT7621_SYSC_BASE IOMEM(0x1E000000)
17 #define SYSC_REG_CHIP_NAME0 0x00
18 #define SYSC_REG_CHIP_NAME1 0x04
19 #define SYSC_REG_CHIP_REV 0x0c
20 #define SYSC_REG_SYSTEM_CONFIG0 0x10
21 #define SYSC_REG_SYSTEM_CONFIG1 0x14
23 #define CHIP_REV_PKG_MASK 0x1
25 #define CHIP_REV_VER_MASK 0xf
[all …]
/openbmc/linux/drivers/video/
H A Dsticore.c66 * 0 - Black
79 0, 6, 4, 5,
85 #define c_index(sti, c) ((c) & 0xff)
107 memset(inptr, 0, sizeof(*inptr)); in sti_init_graph()
109 memset(inptr_ext, 0, sizeof(*inptr_ext)); in sti_init_graph()
111 outptr->errno = 0; in sti_init_graph()
116 if (ret >= 0) in sti_init_graph()
122 if (ret < 0) { in sti_init_graph()
127 return 0; in sti_init_graph()
145 memset(inptr, 0, sizeof(*inptr)); in sti_inq_conf()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
/openbmc/linux/arch/mips/kernel/
H A Drelocate.c44 return 0; in plat_post_relocation()
51 __asm__("rdhwr %0, $1" : "=r" (res)); in get_synci_step()
63 "synci 0(%0)" in sync_icache()
86 unsigned long target_addr = (*loc_orig) & 0x03ffffff; in apply_r_mips_26_rel()
95 target_addr += (unsigned long)loc_orig & 0xf0000000; in apply_r_mips_26_rel()
100 if ((target_addr & 0xf0000000) != ((unsigned long)loc_new & 0xf0000000)) { in apply_r_mips_26_rel()
105 target_addr -= (unsigned long)loc_new & 0xf0000000; in apply_r_mips_26_rel()
108 *loc_new = (*loc_new & ~0x03ffffff) | (target_addr & 0x03ffffff); in apply_r_mips_26_rel()
110 return 0; in apply_r_mips_26_rel()
118 unsigned long target = (insn & 0xffff) << 16; /* high 16bits of target */ in apply_r_mips_hi16_rel()
[all …]
H A Dmodule.c39 GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, in module_alloc()
40 __builtin_return_address(0)); in module_alloc()
58 if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { in apply_r_mips_26()
64 *location = (*location & ~0x03ffffff) | in apply_r_mips_26()
65 ((base + (v >> 2)) & 0x03ffffff); in apply_r_mips_26()
67 return 0; in apply_r_mips_26()
76 *location = (*location & 0xffff0000) | in apply_r_mips_hi16()
77 ((((long long) v + 0x8000LL) >> 16) & 0xffff); in apply_r_mips_hi16()
78 return 0; in apply_r_mips_hi16()
95 return 0; in apply_r_mips_hi16()
[all …]
H A Dftrace.c40 #define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */
41 #define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */
44 #define INSN_NOP 0x00000000 /* nop */
59 buf = (u32 *)&insn_la_mcount[0]; in ftrace_dyn_arch_init_insns()
85 return 0; in ftrace_modify_code()
106 return 0; in ftrace_modify_code_2()
126 return 0; in ftrace_modify_code_2r()
143 * lui v1, hi_16bit_of_mcount --> b 1f (0x10000005)
152 * lui v1, hi_16bit_of_mcount --> b 1f (0x10000004)
160 #define INSN_B_1F (0x10000000 | MCOUNT_OFFSET_INSNS)
[all …]
H A Dvpe.c39 #define ARCH_SHF_SMALL 0
152 memset(addr, 0, len); in alloc_progmem()
192 {ARCH_SHF_SMALL | SHF_ALLOC, 0} in layout_sections()
196 for (i = 0; i < hdr->e_shnum; i++) in layout_sections()
197 sechdrs[i].sh_entsize = ~0UL; in layout_sections()
199 for (m = 0; m < ARRAY_SIZE(masks); ++m) { in layout_sections()
200 for (i = 0; i < hdr->e_shnum; ++i) { in layout_sections()
206 if ((s->sh_flags & masks[m][0]) != masks[m][0] in layout_sections()
208 || s->sh_entsize != ~0UL) in layout_sections()
230 return 0; in apply_r_mips_none()
[all …]
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
/openbmc/linux/arch/openrisc/kernel/
H A Dmodule.c30 for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { in apply_relocate_add()
54 value &= 0x03ffffff; in apply_relocate_add()
55 value |= *location & 0xfc000000; in apply_relocate_add()
65 return 0; in apply_relocate_add()
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dpoly1305-armv4.pl28 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
38 ($ctx,$inp,$len,$padbit)=map("r$_",(0..3));
71 cmp $inp,#0
72 str r3,[$ctx,#0] @ zero hash value
83 moveq r0,#0
94 ldrb r4,[$inp,#0]
95 mov r10,#0x0fffffff
97 and r3,r10,#-4 @ 0x0ffffffc
153 str r4,[$ctx,#0]
164 mov r0,#0
[all …]
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/openbmc/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr25 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
26 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
27 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
30 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
31 0x14000000 - 0x17ffffff(CS5) | I2C | USB
32 0x18000000 - 0x1bffffff(CS6) | reserved | SD
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dflexbus.h94 #define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
96 #define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16)
97 #define FBCS_CSMR_BAM_MASK (0x0000FFFF)
98 #define FBCS_CSMR_BAM_4G (0xFFFF0000)
99 #define FBCS_CSMR_BAM_2G (0x7FFF0000)
100 #define FBCS_CSMR_BAM_1G (0x3FFF0000)
101 #define FBCS_CSMR_BAM_1024M (0x3FFF0000)
102 #define FBCS_CSMR_BAM_512M (0x1FFF0000)
103 #define FBCS_CSMR_BAM_256M (0x0FFF0000)
104 #define FBCS_CSMR_BAM_128M (0x07FF0000)
[all …]
/openbmc/linux/drivers/pcmcia/
H A Dtcic.h33 #define TCIC_BASE 0x240
36 #define TCIC_DATA 0x00
37 #define TCIC_ADDR 0x02
38 #define TCIC_SCTRL 0x06
39 #define TCIC_SSTAT 0x07
40 #define TCIC_MODE 0x08
41 #define TCIC_PWR 0x09
42 #define TCIC_EDC 0x0A
43 #define TCIC_ICSR 0x0C
44 #define TCIC_IENA 0x0D
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/openbmc/linux/fs/unicode/
H A Dutf8-norm.c13 while (i >= 0 && um->tables->utf8agetab[i] != 0) { in utf8version_is_supported()
18 return 0; in utf8version_is_supported()
28 * 0x00000000 0x0000007F: 0xxxxxxx
29 * 0x00000000 0x000007FF: 110xxxxx 10xxxxxx
30 * 0x00000000 0x0000FFFF: 1110xxxx 10xxxxxx 10xxxxxx
31 * 0x00000000 0x001FFFFF: 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx
32 * 0x00000000 0x03FFFFFF: 111110xx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
33 * 0x00000000 0x7FFFFFFF: 1111110x 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
40 * 0x00000000 0x0000007F: 0xxxxxxx
41 * 0x00000080 0x000007FF: 110xxxxx 10xxxxxx
[all …]
/openbmc/linux/drivers/acpi/acpica/
H A Dexdebug.c73 if (!((level > 0) && index == 0)) { in acpi_ex_do_debug_object()
83 timer &= 0x03FFFFFF; in acpi_ex_do_debug_object()
85 acpi_os_printf("ACPI Debug: T=0x%8.8X %*s", timer, in acpi_ex_do_debug_object()
94 if (index > 0) { in acpi_ex_do_debug_object()
139 acpi_os_printf("0x%8.8X\n", in acpi_ex_do_debug_object()
142 acpi_os_printf("0x%8.8X%8.8X\n", in acpi_ex_do_debug_object()
150 acpi_os_printf("[0x%.2X]\n", (u32)source_desc->buffer.length); in acpi_ex_do_debug_object()
154 DB_BYTE_DISPLAY, 0); in acpi_ex_do_debug_object()
164 acpi_os_printf("(Contains 0x%.2X Elements):\n", in acpi_ex_do_debug_object()
169 for (i = 0; i < source_desc->package.count; i++) { in acpi_ex_do_debug_object()
[all …]
/openbmc/qemu/include/libdecnumber/
H A DdecNumberLocal.h50 /* 1=little-endian, 0=big-endian */
52 #define DECLITEND 0
58 #define DECUSE64 1 /* 1=use int64s, 0=int32 & smaller only */
60 /* Conditional check flags -- set these to 0 for best performance */
61 #define DECCHECK 0 /* 1 to enable robust checking */
62 #define DECALLOC 0 /* 1 to enable memory accounting */
63 #define DECTRACE 0 /* 1 to trace certain internals, etc. */
92 #define DECNOINT 0 /* 1 to check no internal use of 'int' */
103 extern const uShort DPD2BIN[1024]; /* DPD -> 0-999 */
104 extern const uShort BIN2DPD[1000]; /* 0-999 -> DPD */
[all …]
/openbmc/u-boot/board/renesas/alt/
H A Dalt_spl.c26 #define SD1CKCR 0xE6150078
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Dpoly1305-p10le_64.S16 # clamp r &= 0x0FFFFFFC0FFFFFFC 0x0FFFFFFC0FFFFFFF
93 mflr 0
94 std 0, 16(1)
117 SAVE_VRS 20, 0, 9
152 RESTORE_VRS 20, 0, 9
204 ld 0, 16(1)
205 mtlr 0
209 # p[0] = a0*r0 + a1*r4*5 + a2*r3*5 + a3*r2*5 + a4*r1*5;
224 vmulouw 13, 8, 0
272 vmuleuw 13, 8, 0
[all …]
/openbmc/u-boot/board/renesas/silk/
H A Dsilk_spl.c26 #define SD1CKCR 0xE6150078
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]

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