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Searched +full:0 +full:x02004000 (Results 1 – 18 of 18) sorted by relevance

/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dhardware-k2hk.h15 #define KS2_PASS_BASE 0x02000000
18 #define KS2_LPSC_MOD 0
73 #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
74 #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
75 #define KS2_DDR3B_DDRPHYC 0x02328000
77 #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */
78 #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2
88 #define KS2_NETCP_PDMA_CTRL_BASE 0x02004000
89 #define KS2_NETCP_PDMA_TX_BASE 0x02004400
91 #define KS2_NETCP_PDMA_RX_BASE 0x02004800
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dg84.c28 { 0x04008000, NVKM_ENGINE_BSP },
29 { 0x02004000, NVKM_ENGINE_CIPHER },
30 { 0x01020000, NVKM_ENGINE_VP },
31 { 0x00400002, NVKM_ENGINE_MPEG },
32 { 0x00201000, NVKM_ENGINE_GR },
33 { 0x00000100, NVKM_ENGINE_FIFO },
39 { NVKM_ENGINE_DISP , 0, 0, 0x04000000, true },
40 { NVKM_ENGINE_VP , 0, 0, 0x00020000, true },
41 { NVKM_ENGINE_BSP , 0, 0, 0x00008000, true },
42 { NVKM_ENGINE_CIPHER, 0, 0, 0x00004000, true },
[all …]
H A Dg98.c28 { 0x04008000, NVKM_ENGINE_MSVLD },
29 { 0x02004000, NVKM_ENGINE_SEC },
30 { 0x01020000, NVKM_ENGINE_MSPDEC },
31 { 0x00400002, NVKM_ENGINE_MSPPP },
32 { 0x00201000, NVKM_ENGINE_GR },
33 { 0x00000100, NVKM_ENGINE_FIFO },
39 { NVKM_ENGINE_DISP , 0, 0, 0x04000000, true },
40 { NVKM_ENGINE_MSPDEC, 0, 0, 0x00020000, true },
41 { NVKM_ENGINE_MSVLD , 0, 0, 0x00008000, true },
42 { NVKM_ENGINE_SEC , 0, 0, 0x00004000, true },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,spdif.yaml104 reg = <0x02004000 0x4000>;
105 interrupts = <0 52 0x04>;
106 dmas = <&sdma 14 18 0>,
107 <&sdma 15 18 0>;
111 <&clks 0>, <&clks 118>,
113 <&clks 0>;
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx6ul.h97 FSL_IMX6UL_MMDC_ADDR = 0x80000000,
100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
116 FSL_IMX6UL_UART6_ADDR = 0x021FC000,
118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
120 FSL_IMX6UL_UART5_ADDR = 0x021F4000,
121 FSL_IMX6UL_UART4_ADDR = 0x021F0000,
[all …]
H A Dfsl-imx6.h84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_2p2_initvals.h25 {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
26 {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
27 {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
28 {0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
29 {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
30 {0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
31 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
32 {0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
33 {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
38 {0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sll.dtsi44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
85 reg = <0x00a01000 0x1000>,
86 <0x00a00100 0x100>;
92 #size-cells = <0>;
94 ckil: clock@0 {
96 reg = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
[all …]
H A Dimx6sl.dtsi24 memory { device_type = "memory"; reg = <0 0>; };
48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0x0>;
83 reg = <0x00a01000 0x1000>,
84 <0x00a00100 0x100>;
90 #size-cells = <0>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
114 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6qdl.dtsi56 #clock-cells = <0>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
84 #size-cells = <0>;
89 lvds-channel@0 {
91 #size-cells = <0>;
92 reg = <0>;
95 port@0 {
[all …]
H A Dimx6sx.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
94 reg = <0x00a01000 0x1000>,
95 <0x00a00100 0x100>;
101 #size-cells = <0>;
103 ckil: clock@0 {
105 reg = <0>;
106 #clock-cells = <0>;
114 #clock-cells = <0>;
[all …]
H A Dimx6ull.dtsi53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0>;
90 reg = <0x00a01000 0x1000>,
91 <0x00a02000 0x100>;
96 #size-cells = <0>;
98 ckil: clock@0 {
100 reg = <0>;
101 #clock-cells = <0>;
109 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
97 clock-frequency = <0>;
103 #clock-cells = <0>;
104 clock-frequency = <0>;
117 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6sl.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
86 #clock-cells = <0>;
92 #clock-cells = <0>;
100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
105 #phy-cells = <0>;
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
128 reg = <0x00a01000 0x1000>,
[all …]
H A Dimx6qdl.dtsi59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
[all …]
H A Dimx6sx.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]