Lines Matching +full:0 +full:x02004000
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0>;
90 reg = <0x00a01000 0x1000>,
91 <0x00a02000 0x100>;
96 #size-cells = <0>;
98 ckil: clock@0 {
100 reg = <0>;
101 #clock-cells = <0>;
109 #clock-cells = <0>;
117 #clock-cells = <0>;
118 clock-frequency = <0>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
166 reg = <0x00900000 0x4000>;
171 reg = <0x00904000 0x1000>;
176 reg = <0x00905000 0x1B000>;
181 reg = <0x01804000 0x2000>;
196 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
207 dmas = <&dma_apbh 0>;
216 reg = <0x02000000 0x100000>;
223 reg = <0x02000000 0x40000>;
228 reg = <0x02004000 0x4000>;
230 dmas = <&sdma 41 18 0>,
231 <&sdma 42 18 0>;
250 #size-cells = <0>;
252 reg = <0x02008000 0x4000>;
264 #size-cells = <0>;
266 reg = <0x0200c000 0x4000>;
278 #size-cells = <0>;
280 reg = <0x02010000 0x4000>;
292 #size-cells = <0>;
294 reg = <0x02014000 0x4000>;
307 reg = <0x02018000 0x4000>;
312 dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
320 reg = <0x02020000 0x4000>;
330 reg = <0x02024000 0x4000>;
339 dmas = <&sdma 0 21 0>, <&sdma 47 21 0>;
341 dma-source = <&gpr 0 14 0 15>;
348 reg = <0x02028000 0x4000>;
353 <&clks 0>, <&clks 0>;
356 dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
363 reg = <0x0202c000 0x4000>;
368 <&clks 0>, <&clks 0>;
371 dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
378 reg = <0x02030000 0x4000>;
383 <&clks 0>, <&clks 0>;
386 dmas = <&sdma 39 24 0>, <&sdma 40 24 0>;
392 reg = <0x02034000 0x4000>;
395 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
396 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
397 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
398 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
399 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
418 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
429 reg = <0x02080000 0x4000>;
439 reg = <0x02084000 0x4000>;
449 reg = <0x02088000 0x4000>;
459 reg = <0x0208c000 0x4000>;
469 reg = <0x02090000 0x4000>;
474 stop-mode = <&gpr 0x10 1 0x10 17>;
480 reg = <0x02094000 0x4000>;
485 stop-mode = <&gpr 0x10 2 0x10 18>;
491 reg = <0x02098000 0x4000>;
500 reg = <0x0209c000 0x4000>;
511 reg = <0x020a0000 0x4000>;
522 reg = <0x020a4000 0x4000>;
533 reg = <0x020a8000 0x4000>;
544 reg = <0x020ac000 0x4000>;
555 reg = <0x020b0000 0x4000>;
561 reg = <0x020b4000 0x4000>;
571 stop-mode = <&gpr 0x10 4>;
575 fsl,wakeup_irq = <0>;
581 reg = <0x020b8000 0x4000>;
589 reg = <0x020bc000 0x4000>;
596 reg = <0x020c0000 0x4000>;
604 reg = <0x020c4000 0x4000>;
615 reg = <0x020c8000 0x1000>;
625 anatop-reg-offset = <0x120>;
628 anatop-min-bit-val = <0>;
631 anatop-enable-bit = <0>;
640 anatop-reg-offset = <0x140>;
641 anatop-vol-bit-shift = <0>;
643 anatop-delay-reg-offset = <0x170>;
657 anatop-reg-offset = <0x140>;
660 anatop-delay-reg-offset = <0x170>;
671 reg = <0x020c9000 0x1000>;
680 reg = <0x020ca000 0x1000>;
696 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
697 reg = <0x020cc000 0x4000>;
700 compatible = "fsl,sec-v4.0-mon-rtc-lp";
702 offset = <0x34>;
709 offset = <0x38>;
710 mask = <0x61>;
714 compatible = "fsl,sec-v4.0-pwrkey";
723 reg = <0x020d0000 0x4000>;
728 reg = <0x020d4000 0x4000>;
734 reg = <0x020d8000 0x4000>;
742 reg = <0x020dc000 0x4000>;
747 fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>;
752 reg = <0x020e0000 0x4000>;
757 reg = <0x020e4000 0x4000>;
768 reg = <0x020e8000 0x4000>;
777 reg = <0x020ec000 0x4000>;
789 reg = <0x020f0000 0x4000>;
799 reg = <0x020f4000 0x4000>;
809 reg = <0x020f8000 0x4000>;
819 reg = <0x020fc000 0x4000>;
832 reg = <0x02100000 0x100000>;
837 reg = <0x02184000 0x200>;
841 fsl,usbmisc = <&usbmisc 0>;
843 ahb-burst-config = <0x0>;
844 tx-burst-size-dword = <0x10>;
845 rx-burst-size-dword = <0x10>;
851 reg = <0x02184200 0x200>;
856 ahb-burst-config = <0x0>;
857 tx-burst-size-dword = <0x10>;
858 rx-burst-size-dword = <0x10>;
865 reg = <0x02184800 0x200>;
870 reg = <0x02188000 0x4000>;
880 stop-mode = <&gpr 0x10 3>;
884 fsl,wakeup_irq = <0>;
890 reg = <0x02190000 0x4000>;
903 reg = <0x02194000 0x4000>;
916 reg = <0x02198000 0x4000>;
926 #size-cells = <0>;
928 reg = <0x021a0000 0x4000>;
936 #size-cells = <0>;
938 reg = <0x021a4000 0x4000>;
946 #size-cells = <0>;
948 reg = <0x021a8000 0x4000>;
956 reg = <0x021ac000 0x4000>;
961 reg = <0x021b0000 0x4000>;
966 reg = <0x021b8000 0x4000>;
973 reg = <0x021bc000 0x4000>;
979 reg = <0x021c0000 0x4000>;
986 reg = <0x021c4000 0x4000>;
997 reg = <0x021c8000 0x4000>;
1008 reg = <0x021cc000 0x4000>;
1018 #size-cells = <0>;
1020 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1031 reg = <0x021e4000 0x4000>;
1040 reg = <0x021e8000 0x4000>;
1045 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1053 reg = <0x021ec000 0x4000>;
1058 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1066 reg = <0x021f0000 0x4000>;
1071 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1079 reg = <0x021f4000 0x4000>;
1084 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1091 #size-cells = <0>;
1093 reg = <0x021f8000 0x4000>;
1102 reg = <0x021fc000 0x4000>;
1107 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1117 reg = <0x02200000 0x100000>;
1121 reg = <0x02280000 0x4000>;
1131 reg = <0x02284000 0x4000>;
1138 reg = <0x02288000 0x4000>;
1143 dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
1151 reg = <0x0228c000 0x4000>;
1156 /* epdc-ram = <&gpr 0x4 30>; */
1162 reg = <0x02290000 0x10000>;
1165 snvs_gpr: snvs-gpr@0x02294000 {
1167 reg = <0x02294000 0x10000>;