1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2dc7de222SMasahiro Yamada /* 3dc7de222SMasahiro Yamada * K2HK: SoC definitions 4dc7de222SMasahiro Yamada * 5dc7de222SMasahiro Yamada * (C) Copyright 2012-2014 6dc7de222SMasahiro Yamada * Texas Instruments Incorporated, <www.ti.com> 7dc7de222SMasahiro Yamada */ 8dc7de222SMasahiro Yamada 9dc7de222SMasahiro Yamada #ifndef __ASM_ARCH_HARDWARE_K2HK_H 10dc7de222SMasahiro Yamada #define __ASM_ARCH_HARDWARE_K2HK_H 11dc7de222SMasahiro Yamada 12dc7de222SMasahiro Yamada #define KS2_ARM_PLL_EN BIT(13) 13dc7de222SMasahiro Yamada 14dc7de222SMasahiro Yamada /* PA SS Registers */ 15dc7de222SMasahiro Yamada #define KS2_PASS_BASE 0x02000000 16dc7de222SMasahiro Yamada 17dc7de222SMasahiro Yamada /* Power and Sleep Controller (PSC) Domains */ 18dc7de222SMasahiro Yamada #define KS2_LPSC_MOD 0 19dc7de222SMasahiro Yamada #define KS2_LPSC_DUMMY1 1 20dc7de222SMasahiro Yamada #define KS2_LPSC_USB 2 21dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF25_SPI 3 22dc7de222SMasahiro Yamada #define KS2_LPSC_TSIP 4 23dc7de222SMasahiro Yamada #define KS2_LPSC_DEBUGSS_TRC 5 24dc7de222SMasahiro Yamada #define KS2_LPSC_TETB_TRC 6 25dc7de222SMasahiro Yamada #define KS2_LPSC_PKTPROC 7 26dc7de222SMasahiro Yamada #define KS2_LPSC_PA KS2_LPSC_PKTPROC 27dc7de222SMasahiro Yamada #define KS2_LPSC_SGMII 8 28dc7de222SMasahiro Yamada #define KS2_LPSC_CPGMAC KS2_LPSC_SGMII 29dc7de222SMasahiro Yamada #define KS2_LPSC_CRYPTO 9 30dc7de222SMasahiro Yamada #define KS2_LPSC_PCIE 10 31dc7de222SMasahiro Yamada #define KS2_LPSC_SRIO 11 32dc7de222SMasahiro Yamada #define KS2_LPSC_VUSR0 12 33dc7de222SMasahiro Yamada #define KS2_LPSC_CHIP_SRSS 13 34dc7de222SMasahiro Yamada #define KS2_LPSC_MSMC 14 35dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_1 16 36dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_2 17 37dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_3 18 38dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_4 19 39dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_5 20 40dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_6 21 41dc7de222SMasahiro Yamada #define KS2_LPSC_GEM_7 22 42dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF4F_DDR3A 23 43dc7de222SMasahiro Yamada #define KS2_LPSC_EMIF4F_DDR3B 24 44dc7de222SMasahiro Yamada #define KS2_LPSC_TAC 25 45dc7de222SMasahiro Yamada #define KS2_LPSC_RAC 26 46dc7de222SMasahiro Yamada #define KS2_LPSC_RAC_1 27 47dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_A 28 48dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_B 29 49dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_C 30 50dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_D 31 51dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_E 32 52dc7de222SMasahiro Yamada #define KS2_LPSC_FFTC_F 33 53dc7de222SMasahiro Yamada #define KS2_LPSC_AI2 34 54dc7de222SMasahiro Yamada #define KS2_LPSC_TCP3D_0 35 55dc7de222SMasahiro Yamada #define KS2_LPSC_TCP3D_1 36 56dc7de222SMasahiro Yamada #define KS2_LPSC_TCP3D_2 37 57dc7de222SMasahiro Yamada #define KS2_LPSC_TCP3D_3 38 58dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_A 39 59dc7de222SMasahiro Yamada #define KS2_LPSC_CP2X4_B 40 60dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_C 41 61dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_D 42 62dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_E 43 63dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_F 44 64dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_G 45 65dc7de222SMasahiro Yamada #define KS2_LPSC_VCP2X4_H 46 66dc7de222SMasahiro Yamada #define KS2_LPSC_BCP 47 67dc7de222SMasahiro Yamada #define KS2_LPSC_DXB 48 68dc7de222SMasahiro Yamada #define KS2_LPSC_VUSR1 49 69dc7de222SMasahiro Yamada #define KS2_LPSC_XGE 50 70dc7de222SMasahiro Yamada #define KS2_LPSC_ARM_SREFLEX 51 71dc7de222SMasahiro Yamada 72dc7de222SMasahiro Yamada /* DDR3B definitions */ 73dc7de222SMasahiro Yamada #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 74dc7de222SMasahiro Yamada #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 75dc7de222SMasahiro Yamada #define KS2_DDR3B_DDRPHYC 0x02328000 76dc7de222SMasahiro Yamada 77dc7de222SMasahiro Yamada #define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ 78dc7de222SMasahiro Yamada #define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 79dc7de222SMasahiro Yamada channel 29 */ 80dc7de222SMasahiro Yamada 81dc7de222SMasahiro Yamada /* SGMII SerDes */ 82dc7de222SMasahiro Yamada #define KS2_LANES_PER_SGMII_SERDES 4 83dc7de222SMasahiro Yamada 84dc7de222SMasahiro Yamada /* Number of DSP cores */ 85dc7de222SMasahiro Yamada #define KS2_NUM_DSPS 8 86dc7de222SMasahiro Yamada 87dc7de222SMasahiro Yamada /* NETCP pktdma */ 88dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_CTRL_BASE 0x02004000 89dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_BASE 0x02004400 90dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_CH_NUM 9 91dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_BASE 0x02004800 92dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_CH_NUM 26 93dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 94dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 95dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_RX_FLOW_NUM 32 96dc7de222SMasahiro Yamada #define KS2_NETCP_PDMA_TX_SND_QUEUE 648 97dc7de222SMasahiro Yamada 98dc7de222SMasahiro Yamada /* NETCP */ 99dc7de222SMasahiro Yamada #define KS2_NETCP_BASE 0x02000000 100dc7de222SMasahiro Yamada 101dc7de222SMasahiro Yamada #endif /* __ASM_ARCH_HARDWARE_H */ 102