Lines Matching +full:0 +full:x02004000
56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
94 reg = <0x00a01000 0x1000>,
95 <0x00a00100 0x100>;
101 #size-cells = <0>;
103 ckil: clock@0 {
105 reg = <0>;
106 #clock-cells = <0>;
114 #clock-cells = <0>;
122 #clock-cells = <0>;
123 clock-frequency = <0>;
130 #clock-cells = <0>;
131 clock-frequency = <0>;
150 reg = <0x00900000 0x20000>;
156 reg = <0x00a02000 0x1000>;
166 reg = <0x01800000 0x4000>;
176 reg = <0x01804000 0x2000>;
191 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
202 dmas = <&dma_apbh 0>;
211 reg = <0x02000000 0x100000>;
218 reg = <0x02000000 0x40000>;
223 reg = <0x02004000 0x4000>;
225 dmas = <&sdma 14 18 0>,
226 <&sdma 15 18 0>;
231 <&clks 0>, <&clks 0>, <&clks 0>,
233 <&clks 0>, <&clks 0>,
245 #size-cells = <0>;
247 reg = <0x02008000 0x4000>;
257 #size-cells = <0>;
259 reg = <0x0200c000 0x4000>;
269 #size-cells = <0>;
271 reg = <0x02010000 0x4000>;
281 #size-cells = <0>;
283 reg = <0x02014000 0x4000>;
293 reg = <0x02020000 0x4000>;
298 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
304 reg = <0x02024000 0x4000>;
317 #sound-dai-cells = <0>;
319 reg = <0x02028000 0x4000>;
324 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
331 #sound-dai-cells = <0>;
333 reg = <0x0202c000 0x4000>;
338 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
345 #sound-dai-cells = <0>;
347 reg = <0x02030000 0x4000>;
352 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
359 reg = <0x02034000 0x4000>;
377 reg = <0x02080000 0x4000>;
387 reg = <0x02084000 0x4000>;
397 reg = <0x02088000 0x4000>;
407 reg = <0x0208c000 0x4000>;
417 reg = <0x02090000 0x4000>;
427 reg = <0x02094000 0x4000>;
437 reg = <0x02098000 0x4000>;
446 reg = <0x0209c000 0x4000>;
453 gpio-ranges = <&iomuxc 0 5 26>;
458 reg = <0x020a0000 0x4000>;
465 gpio-ranges = <&iomuxc 0 31 20>;
470 reg = <0x020a4000 0x4000>;
477 gpio-ranges = <&iomuxc 0 51 29>;
482 reg = <0x020a8000 0x4000>;
489 gpio-ranges = <&iomuxc 0 80 32>;
494 reg = <0x020ac000 0x4000>;
501 gpio-ranges = <&iomuxc 0 112 24>;
506 reg = <0x020b0000 0x4000>;
513 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
518 reg = <0x020b4000 0x4000>;
525 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
530 reg = <0x020b8000 0x4000>;
538 reg = <0x020bc000 0x4000>;
545 reg = <0x020c0000 0x4000>;
553 reg = <0x020c4000 0x4000>;
564 reg = <0x020c8000 0x1000>;
575 anatop-reg-offset = <0x110>;
589 anatop-reg-offset = <0x120>;
592 anatop-min-bit-val = <0>;
603 anatop-reg-offset = <0x130>;
606 anatop-min-bit-val = <0>;
617 anatop-reg-offset = <0x140>;
618 anatop-vol-bit-shift = <0>;
620 anatop-delay-reg-offset = <0x170>;
633 anatop-reg-offset = <0x140>;
636 anatop-delay-reg-offset = <0x170>;
650 anatop-reg-offset = <0x140>;
653 anatop-delay-reg-offset = <0x170>;
672 reg = <0x020c9000 0x1000>;
680 reg = <0x020ca000 0x1000>;
687 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
688 reg = <0x020cc000 0x4000>;
691 compatible = "fsl,sec-v4.0-mon-rtc-lp";
693 offset = <0x34>;
700 offset = <0x38>;
701 mask = <0x60>;
706 compatible = "fsl,sec-v4.0-pwrkey";
715 reg = <0x020d0000 0x4000>;
720 reg = <0x020d4000 0x4000>;
726 reg = <0x020d8000 0x4000>;
734 reg = <0x020dc000 0x4000>;
743 reg = <0x020e0000 0x4000>;
749 reg = <0x020e4000 0x4000>;
754 reg = <0x020ec000 0x4000>;
769 reg = <0x02100000 0x100000>;
773 compatible = "fsl,sec-v4.0";
777 reg = <0x2100000 0x10000>;
778 ranges = <0 0x2100000 0x10000>;
787 compatible = "fsl,sec-v4.0-job-ring";
788 reg = <0x1000 0x1000>;
793 compatible = "fsl,sec-v4.0-job-ring";
794 reg = <0x2000 0x1000>;
801 reg = <0x02184000 0x200>;
805 fsl,usbmisc = <&usbmisc 0>;
807 ahb-burst-config = <0x0>;
808 tx-burst-size-dword = <0x10>;
809 rx-burst-size-dword = <0x10>;
815 reg = <0x02184200 0x200>;
820 ahb-burst-config = <0x0>;
821 tx-burst-size-dword = <0x10>;
822 rx-burst-size-dword = <0x10>;
828 reg = <0x02184400 0x200>;
835 ahb-burst-config = <0x0>;
836 tx-burst-size-dword = <0x10>;
837 rx-burst-size-dword = <0x10>;
844 reg = <0x02184800 0x200>;
850 reg = <0x02188000 0x4000>;
866 reg = <0x0218c000 0x4000>;
876 reg = <0x02190000 0x4000>;
888 reg = <0x02194000 0x4000>;
900 reg = <0x02198000 0x4000>;
912 reg = <0x0219c000 0x4000>;
924 #size-cells = <0>;
926 reg = <0x021a0000 0x4000>;
934 #size-cells = <0>;
936 reg = <0x021a4000 0x4000>;
944 #size-cells = <0>;
946 reg = <0x021a8000 0x4000>;
954 reg = <0x021b0000 0x4000>;
959 reg = <0x021b4000 0x4000>;
974 reg = <0x021b8000 0x4000>;
981 reg = <0x021bc000 0x4000>;
987 reg = <0x021d4000 0x4000>;
991 <&clks 0>, <&clks 0>;
994 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1000 reg = <0x021d8000 0x4000>;
1006 reg = <0x021dc000 0x4000>;
1010 <&clks 0>, <&clks 0>;
1013 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1019 #size-cells = <0>;
1021 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1032 #size-cells = <0>;
1034 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1045 reg = <0x021e8000 0x4000>;
1050 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1057 reg = <0x021ec000 0x4000>;
1062 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1069 reg = <0x021f0000 0x4000>;
1074 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1081 reg = <0x021f4000 0x4000>;
1086 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1093 #size-cells = <0>;
1095 reg = <0x021f8000 0x4000>;
1106 reg = <0x02200000 0x100000>;
1113 reg = <0x02240000 0x40000>;
1117 reg = <0x02214000 0x4000>;
1127 reg = <0x02218000 0x4000>;
1136 reg = <0x0221c000 0x4000>;
1147 reg = <0x02220000 0x4000>;
1158 reg = <0x02224000 0x4000>;
1168 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1179 reg = <0x02280000 0x4000>;
1190 reg = <0x02284000 0x4000>;
1201 reg = <0x02288000 0x4000>;
1209 #size-cells = <0>;
1211 reg = <0x0228c000 0x4000>;
1221 reg = <0x022a0000 0x4000>;
1226 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1233 reg = <0x022a4000 0x4000>;
1243 reg = <0x022a8000 0x4000>;
1253 reg = <0x022ac000 0x4000>;
1263 reg = <0x0022b0000 0x4000>;
1272 pcie: pcie@0x08000000 {
1274 reg = <0x08ffc000 0x4000>; /* DBI */
1279 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1281 0x81000000 0 0 0x08f80000 0 0x00010000
1283 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;