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/openbmc/linux/drivers/mtd/chips/
H A Djedec_probe.c27 #define AM29DL800BB 0x22CB
28 #define AM29DL800BT 0x224A
30 #define AM29F800BB 0x2258
31 #define AM29F800BT 0x22D6
32 #define AM29LV400BB 0x22BA
33 #define AM29LV400BT 0x22B9
34 #define AM29LV800BB 0x225B
35 #define AM29LV800BT 0x22DA
36 #define AM29LV160DT 0x22C4
37 #define AM29LV160DB 0x2249
[all …]
/openbmc/u-boot/drivers/mtd/
H A Djedec_flash.c23 #define AM29DL800BB 0x22CB
24 #define AM29DL800BT 0x224A
26 #define AM29F400BB 0x22AB
27 #define AM29F800BB 0x2258
28 #define AM29F800BT 0x22D6
29 #define AM29LV400BB 0x22BA
30 #define AM29LV400BT 0x22B9
31 #define AM29LV800BB 0x225B
32 #define AM29LV800BT 0x22DA
33 #define AM29LV160DT 0x22C4
[all …]
/openbmc/linux/arch/mips/include/uapi/asm/
H A Dtermbits.h55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
/openbmc/linux/arch/parisc/include/uapi/asm/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/linux/include/uapi/asm-generic/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/openbmc/linux/arch/sparc/include/uapi/asm/
H A Dtermbits.h51 #define VINTR 0
78 #define IUCLC 0x0200
79 #define IXON 0x0400
80 #define IXOFF 0x1000
81 #define IMAXBEL 0x2000
82 #define IUTF8 0x4000
85 #define OLCUC 0x00002
86 #define ONLCR 0x00004
87 #define NLDLY 0x00100
88 #define NL0 0x00000
[all …]
/openbmc/qemu/linux-user/alpha/
H A Dtarget_mman.h4 #define TARGET_MAP_ANONYMOUS 0x10
5 #define TARGET_MAP_FIXED 0x100
6 #define TARGET_MAP_GROWSDOWN 0x01000
7 #define TARGET_MAP_DENYWRITE 0x02000
8 #define TARGET_MAP_EXECUTABLE 0x04000
9 #define TARGET_MAP_LOCKED 0x08000
10 #define TARGET_MAP_NORESERVE 0x10000
11 #define TARGET_MAP_POPULATE 0x20000
12 #define TARGET_MAP_NONBLOCK 0x40000
13 #define TARGET_MAP_STACK 0x80000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/
H A Dimx-regs.h9 #define LPUART_BASE 0x5A060000
11 #define GPT1_BASE_ADDR 0x5D140000
12 #define SCU_LPUART_BASE 0x33220000
13 #define GPIO1_BASE_ADDR 0x5D080000
14 #define GPIO2_BASE_ADDR 0x5D090000
15 #define GPIO3_BASE_ADDR 0x5D0A0000
16 #define GPIO4_BASE_ADDR 0x5D0B0000
17 #define GPIO5_BASE_ADDR 0x5D0C0000
18 #define GPIO6_BASE_ADDR 0x5D0D0000
19 #define GPIO7_BASE_ADDR 0x5D0E0000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i3c/
H A Dsnps,dw-i3c-master.yaml41 #size-cells = <0>;
42 reg = <0x02000 0x1000>;
43 interrupts = <0>;
48 reg = <0x57 0x0 0x10>;
49 pagesize = <0x8>;
/openbmc/linux/tools/arch/alpha/include/uapi/asm/
H A Dmman.h13 #define MADV_NORMAL 0
19 #define MAP_ANONYMOUS 0x10
20 #define MAP_DENYWRITE 0x02000
21 #define MAP_EXECUTABLE 0x04000
22 #define MAP_FILE 0
23 #define MAP_FIXED 0x100
24 #define MAP_GROWSDOWN 0x01000
25 #define MAP_HUGETLB 0x100000
26 #define MAP_LOCKED 0x08000
27 #define MAP_NONBLOCK 0x40000
[all …]
/openbmc/linux/arch/x86/events/
H A Dperf_event_flags.h5 PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
6 PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
7 PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
8 PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
9 PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
10 PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
11 PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
12 /* 0x00080 */
13 PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
14 PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
[all …]
/openbmc/linux/arch/alpha/include/asm/
H A Dsetup.h12 #define BOOT_PCB 0x20000000
13 #define BOOT_ADDR 0x20000000
18 #define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
20 #define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
25 #define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
26 #define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
27 #define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
28 #define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
30 #define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
39 #define COMMAND_LINE ((char *)(absolute_pointer(PARAM + 0x0000)))
[all …]
/openbmc/qemu/include/hw/misc/
H A Dlasi.h22 #define LASI_IRR 0x00 /* RO */
23 #define LASI_IMR 0x04
24 #define LASI_IPR 0x08
25 #define LASI_ICR 0x0c
26 #define LASI_IAR 0x10
28 #define LASI_LPT 0x02000
29 #define LASI_AUDIO 0x04000
30 #define LASI_UART 0x05000
31 #define LASI_LAN 0x07000
32 #define LASI_RTC 0x09000
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbevf/
H A Dregs.h7 #define IXGBE_VFCTRL 0x00000
8 #define IXGBE_VFSTATUS 0x00008
9 #define IXGBE_VFLINKS 0x00010
10 #define IXGBE_VFFRTIMER 0x00048
11 #define IXGBE_VFRXMEMWRAP 0x03190
12 #define IXGBE_VTEICR 0x00100
13 #define IXGBE_VTEICS 0x00104
14 #define IXGBE_VTEIMS 0x00108
15 #define IXGBE_VTEIMC 0x0010C
16 #define IXGBE_VTEIAC 0x00110
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddisplay2.h94 u8 res[0xc];
112 #define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
113 #define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
115 #define SUNXI_DE2_MUX_GLB_REGS 0x00000
116 #define SUNXI_DE2_MUX_BLD_REGS 0x01000
117 #define SUNXI_DE2_MUX_CHAN_REGS 0x02000
118 #define SUNXI_DE2_MUX_CHAN_SZ 0x1000
119 #define SUNXI_DE2_MUX_VSU_REGS 0x20000
120 #define SUNXI_DE2_MUX_GSU1_REGS 0x30000
121 #define SUNXI_DE2_MUX_GSU2_REGS 0x40000
[all …]
/openbmc/u-boot/include/configs/
H A Dspear-common.h30 #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
35 #define CONFIG_SYS_I2C_BASE 0xD0200000
37 #define CONFIG_SYS_I2C_BASE 0xD0180000
39 #define CONFIG_SYS_I2C_BASE 0xD0180000
41 #define CONFIG_SYS_I2C_BASE 0xD0180000
44 #define CONFIG_SYS_I2C_SLAVE 0x02
46 #define CONFIG_I2C_CHIPADDRESS 0x50
60 #define CONFIG_SYS_FLASH_BASE 0xF8000000
61 #define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
62 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
[all …]
H A DSBx81LIFKW.h18 #define CONFIG_SYS_SDRAM_BASE 0x00000000
52 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
59 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
60 #define CONFIG_ENV_SIZE 0x02000
61 #define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */
87 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
88 #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
89 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
98 #define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
99 #define CONFIG_PHY_BASE_ADR 0x01
[all …]
H A DSBx81LIFXCAT.h18 #define CONFIG_SYS_SDRAM_BASE 0x00000000
52 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
59 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
60 #define CONFIG_ENV_SIZE 0x02000
61 #define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */
87 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
88 #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
89 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
98 #define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
99 #define CONFIG_PHY_BASE_ADR 0x01
[all …]
/openbmc/linux/arch/alpha/include/uapi/asm/
H A Dmman.h5 #define PROT_READ 0x1 /* page can be read */
6 #define PROT_WRITE 0x2 /* page can be written */
7 #define PROT_EXEC 0x4 /* page can be executed */
8 #define PROT_SEM 0x8 /* page may be used for atomic ops */
9 #define PROT_NONE 0x0 /* page can not be accessed */
10 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
11 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
13 /* 0x01 - 0x03 are defined in linux/mman.h */
14 #define MAP_TYPE 0x0f /* Mask for type of mapping (OSF/1 is _wrong_) */
15 #define MAP_FIXED 0x100 /* Interpret addr exactly */
[all …]
H A Dtermbits.h54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_dma.h50 #define NV50_DMA_PUSH_MAX_LENGTH 0x7fffff
53 #define NV50_DMA_IB_MAX ((0x02000 / 8) - 1)
57 NvDmaFB = 0x80000002,
58 NvDmaTT = 0x80000003,
59 NvNotify0 = 0x80000006,
60 NvSema = 0x8000000f,
61 NvEvoSema0 = 0x80000010,
62 NvEvoSema1 = 0x80000011,
75 return 0; in RING_SPACE()
86 nouveau_bo_rd32(chan->push.buffer, 0); \
[all …]
/openbmc/linux/arch/powerpc/include/uapi/asm/
H A Dtermbits.h48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ar7/
H A Dar7.h16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]

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