1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
281b20cccSMichael Schwingen /*
381b20cccSMichael Schwingen * (C) Copyright 2007
481b20cccSMichael Schwingen * Michael Schwingen, <michael@schwingen.org>
581b20cccSMichael Schwingen *
681b20cccSMichael Schwingen * based in great part on jedec_probe.c from linux kernel:
781b20cccSMichael Schwingen * (C) 2000 Red Hat. GPL'd.
881b20cccSMichael Schwingen * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
981b20cccSMichael Schwingen */
1081b20cccSMichael Schwingen
1181b20cccSMichael Schwingen /* The DEBUG define must be before common to enable debugging */
1281b20cccSMichael Schwingen /*#define DEBUG*/
1381b20cccSMichael Schwingen
1481b20cccSMichael Schwingen #include <common.h>
1581b20cccSMichael Schwingen #include <asm/processor.h>
1681b20cccSMichael Schwingen #include <asm/io.h>
1781b20cccSMichael Schwingen #include <asm/byteorder.h>
1881b20cccSMichael Schwingen #include <environment.h>
1981b20cccSMichael Schwingen
2081b20cccSMichael Schwingen #define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY
2181b20cccSMichael Schwingen
2281b20cccSMichael Schwingen /* AMD */
230192d7d5SStefan Roese #define AM29DL800BB 0x22CB
2481b20cccSMichael Schwingen #define AM29DL800BT 0x224A
2581b20cccSMichael Schwingen
263b8b240dSDavid Müller #define AM29F400BB 0x22AB
2781b20cccSMichael Schwingen #define AM29F800BB 0x2258
2881b20cccSMichael Schwingen #define AM29F800BT 0x22D6
2981b20cccSMichael Schwingen #define AM29LV400BB 0x22BA
3081b20cccSMichael Schwingen #define AM29LV400BT 0x22B9
3181b20cccSMichael Schwingen #define AM29LV800BB 0x225B
3281b20cccSMichael Schwingen #define AM29LV800BT 0x22DA
3381b20cccSMichael Schwingen #define AM29LV160DT 0x22C4
3481b20cccSMichael Schwingen #define AM29LV160DB 0x2249
3581b20cccSMichael Schwingen #define AM29F017D 0x003D
3681b20cccSMichael Schwingen #define AM29F016D 0x00AD
3781b20cccSMichael Schwingen #define AM29F080 0x00D5
3881b20cccSMichael Schwingen #define AM29F040 0x00A4
3981b20cccSMichael Schwingen #define AM29LV040B 0x004F
4081b20cccSMichael Schwingen #define AM29F032B 0x0041
4181b20cccSMichael Schwingen #define AM29F002T 0x00B0
4281b20cccSMichael Schwingen
4381b20cccSMichael Schwingen /* SST */
4481b20cccSMichael Schwingen #define SST39LF800 0x2781
4581b20cccSMichael Schwingen #define SST39LF160 0x2782
4681b20cccSMichael Schwingen #define SST39VF1601 0x234b
4781b20cccSMichael Schwingen #define SST39LF512 0x00D4
4881b20cccSMichael Schwingen #define SST39LF010 0x00D5
4981b20cccSMichael Schwingen #define SST39LF020 0x00D6
5081b20cccSMichael Schwingen #define SST39LF040 0x00D7
5181b20cccSMichael Schwingen #define SST39SF010A 0x00B5
5281b20cccSMichael Schwingen #define SST39SF020A 0x00B6
5381b20cccSMichael Schwingen
545e72ef08SDavid Müller (ELSOFT AG) /* STM */
555e72ef08SDavid Müller (ELSOFT AG) #define STM29F400BB 0x00D6
565e72ef08SDavid Müller (ELSOFT AG)
573a7b2c21SNiklaus Giger /* MXIC */
583a7b2c21SNiklaus Giger #define MX29LV040 0x004F
593a7b2c21SNiklaus Giger
603a7b2c21SNiklaus Giger /* WINBOND */
613a7b2c21SNiklaus Giger #define W39L040A 0x00D6
623a7b2c21SNiklaus Giger
633a7b2c21SNiklaus Giger /* AMIC */
643a7b2c21SNiklaus Giger #define A29L040 0x0092
653a7b2c21SNiklaus Giger
663a7b2c21SNiklaus Giger /* EON */
673a7b2c21SNiklaus Giger #define EN29LV040A 0x004F
6881b20cccSMichael Schwingen
6981b20cccSMichael Schwingen /*
7081b20cccSMichael Schwingen * Unlock address sets for AMD command sets.
7181b20cccSMichael Schwingen * Intel command sets use the MTD_UADDR_UNNECESSARY.
7281b20cccSMichael Schwingen * Each identifier, except MTD_UADDR_UNNECESSARY, and
7381b20cccSMichael Schwingen * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
7481b20cccSMichael Schwingen * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
7581b20cccSMichael Schwingen * initialization need not require initializing all of the
7681b20cccSMichael Schwingen * unlock addresses for all bit widths.
7781b20cccSMichael Schwingen */
7881b20cccSMichael Schwingen enum uaddr {
7981b20cccSMichael Schwingen MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
8081b20cccSMichael Schwingen MTD_UADDR_0x0555_0x02AA,
8181b20cccSMichael Schwingen MTD_UADDR_0x0555_0x0AAA,
8281b20cccSMichael Schwingen MTD_UADDR_0x5555_0x2AAA,
8381b20cccSMichael Schwingen MTD_UADDR_0x0AAA_0x0555,
8481b20cccSMichael Schwingen MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
8581b20cccSMichael Schwingen MTD_UADDR_UNNECESSARY, /* Does not require any address */
8681b20cccSMichael Schwingen };
8781b20cccSMichael Schwingen
8881b20cccSMichael Schwingen
8981b20cccSMichael Schwingen struct unlock_addr {
9081b20cccSMichael Schwingen u32 addr1;
9181b20cccSMichael Schwingen u32 addr2;
9281b20cccSMichael Schwingen };
9381b20cccSMichael Schwingen
9481b20cccSMichael Schwingen
9581b20cccSMichael Schwingen /*
9681b20cccSMichael Schwingen * I don't like the fact that the first entry in unlock_addrs[]
9781b20cccSMichael Schwingen * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
9881b20cccSMichael Schwingen * should not be used. The problem is that structures with
9981b20cccSMichael Schwingen * initializers have extra fields initialized to 0. It is _very_
10081b20cccSMichael Schwingen * desireable to have the unlock address entries for unsupported
10181b20cccSMichael Schwingen * data widths automatically initialized - that means that
10281b20cccSMichael Schwingen * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
10381b20cccSMichael Schwingen * must go unused.
10481b20cccSMichael Schwingen */
10581b20cccSMichael Schwingen static const struct unlock_addr unlock_addrs[] = {
10681b20cccSMichael Schwingen [MTD_UADDR_NOT_SUPPORTED] = {
10781b20cccSMichael Schwingen .addr1 = 0xffff,
10881b20cccSMichael Schwingen .addr2 = 0xffff
10981b20cccSMichael Schwingen },
11081b20cccSMichael Schwingen
11181b20cccSMichael Schwingen [MTD_UADDR_0x0555_0x02AA] = {
11281b20cccSMichael Schwingen .addr1 = 0x0555,
11381b20cccSMichael Schwingen .addr2 = 0x02aa
11481b20cccSMichael Schwingen },
11581b20cccSMichael Schwingen
11681b20cccSMichael Schwingen [MTD_UADDR_0x0555_0x0AAA] = {
11781b20cccSMichael Schwingen .addr1 = 0x0555,
11881b20cccSMichael Schwingen .addr2 = 0x0aaa
11981b20cccSMichael Schwingen },
12081b20cccSMichael Schwingen
12181b20cccSMichael Schwingen [MTD_UADDR_0x5555_0x2AAA] = {
12281b20cccSMichael Schwingen .addr1 = 0x5555,
12381b20cccSMichael Schwingen .addr2 = 0x2aaa
12481b20cccSMichael Schwingen },
12581b20cccSMichael Schwingen
12681b20cccSMichael Schwingen [MTD_UADDR_0x0AAA_0x0555] = {
12781b20cccSMichael Schwingen .addr1 = 0x0AAA,
12881b20cccSMichael Schwingen .addr2 = 0x0555
12981b20cccSMichael Schwingen },
13081b20cccSMichael Schwingen
13181b20cccSMichael Schwingen [MTD_UADDR_DONT_CARE] = {
13281b20cccSMichael Schwingen .addr1 = 0x0000, /* Doesn't matter which address */
13381b20cccSMichael Schwingen .addr2 = 0x0000 /* is used - must be last entry */
13481b20cccSMichael Schwingen },
13581b20cccSMichael Schwingen
13681b20cccSMichael Schwingen [MTD_UADDR_UNNECESSARY] = {
13781b20cccSMichael Schwingen .addr1 = 0x0000,
13881b20cccSMichael Schwingen .addr2 = 0x0000
13981b20cccSMichael Schwingen }
14081b20cccSMichael Schwingen };
14181b20cccSMichael Schwingen
14281b20cccSMichael Schwingen
14381b20cccSMichael Schwingen struct amd_flash_info {
14481b20cccSMichael Schwingen const __u16 mfr_id;
14581b20cccSMichael Schwingen const __u16 dev_id;
14681b20cccSMichael Schwingen const char *name;
14781b20cccSMichael Schwingen const int DevSize;
14881b20cccSMichael Schwingen const int NumEraseRegions;
14981b20cccSMichael Schwingen const int CmdSet;
15081b20cccSMichael Schwingen const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
15181b20cccSMichael Schwingen const ulong regions[6];
15281b20cccSMichael Schwingen };
15381b20cccSMichael Schwingen
15481b20cccSMichael Schwingen #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
15581b20cccSMichael Schwingen
15681b20cccSMichael Schwingen #define SIZE_64KiB 16
15781b20cccSMichael Schwingen #define SIZE_128KiB 17
15881b20cccSMichael Schwingen #define SIZE_256KiB 18
15981b20cccSMichael Schwingen #define SIZE_512KiB 19
16081b20cccSMichael Schwingen #define SIZE_1MiB 20
16181b20cccSMichael Schwingen #define SIZE_2MiB 21
16281b20cccSMichael Schwingen #define SIZE_4MiB 22
16381b20cccSMichael Schwingen #define SIZE_8MiB 23
16481b20cccSMichael Schwingen
16581b20cccSMichael Schwingen static const struct amd_flash_info jedec_table[] = {
1666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8
16781b20cccSMichael Schwingen {
16828745db9SStefan Roese .mfr_id = (u16)SST_MANUFACT,
16981b20cccSMichael Schwingen .dev_id = SST39LF020,
17081b20cccSMichael Schwingen .name = "SST 39LF020",
17181b20cccSMichael Schwingen .uaddr = {
17281b20cccSMichael Schwingen [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
17381b20cccSMichael Schwingen },
17481b20cccSMichael Schwingen .DevSize = SIZE_256KiB,
17581b20cccSMichael Schwingen .CmdSet = P_ID_AMD_STD,
17681b20cccSMichael Schwingen .NumEraseRegions= 1,
17781b20cccSMichael Schwingen .regions = {
17881b20cccSMichael Schwingen ERASEINFO(0x01000,64),
17981b20cccSMichael Schwingen }
18081b20cccSMichael Schwingen },
18181b20cccSMichael Schwingen #endif
1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8
18381b20cccSMichael Schwingen {
18428745db9SStefan Roese .mfr_id = (u16)AMD_MANUFACT,
18581b20cccSMichael Schwingen .dev_id = AM29LV040B,
18681b20cccSMichael Schwingen .name = "AMD AM29LV040B",
18781b20cccSMichael Schwingen .uaddr = {
18881b20cccSMichael Schwingen [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
18981b20cccSMichael Schwingen },
19081b20cccSMichael Schwingen .DevSize = SIZE_512KiB,
19181b20cccSMichael Schwingen .CmdSet = P_ID_AMD_STD,
19281b20cccSMichael Schwingen .NumEraseRegions= 1,
19381b20cccSMichael Schwingen .regions = {
19481b20cccSMichael Schwingen ERASEINFO(0x10000,8),
19581b20cccSMichael Schwingen }
19681b20cccSMichael Schwingen },
19781b20cccSMichael Schwingen {
19828745db9SStefan Roese .mfr_id = (u16)SST_MANUFACT,
19981b20cccSMichael Schwingen .dev_id = SST39LF040,
20081b20cccSMichael Schwingen .name = "SST 39LF040",
20181b20cccSMichael Schwingen .uaddr = {
20281b20cccSMichael Schwingen [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
20381b20cccSMichael Schwingen },
20481b20cccSMichael Schwingen .DevSize = SIZE_512KiB,
20581b20cccSMichael Schwingen .CmdSet = P_ID_AMD_STD,
20681b20cccSMichael Schwingen .NumEraseRegions= 1,
20781b20cccSMichael Schwingen .regions = {
20881b20cccSMichael Schwingen ERASEINFO(0x01000,128),
20981b20cccSMichael Schwingen }
21081b20cccSMichael Schwingen },
21194f9279fSNiklaus Giger {
21228745db9SStefan Roese .mfr_id = (u16)STM_MANUFACT,
21394f9279fSNiklaus Giger .dev_id = STM_ID_M29W040B,
21494f9279fSNiklaus Giger .name = "ST Micro M29W040B",
21594f9279fSNiklaus Giger .uaddr = {
21694f9279fSNiklaus Giger [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
21794f9279fSNiklaus Giger },
21894f9279fSNiklaus Giger .DevSize = SIZE_512KiB,
21994f9279fSNiklaus Giger .CmdSet = P_ID_AMD_STD,
22094f9279fSNiklaus Giger .NumEraseRegions= 1,
22194f9279fSNiklaus Giger .regions = {
22294f9279fSNiklaus Giger ERASEINFO(0x10000,8),
22394f9279fSNiklaus Giger }
22494f9279fSNiklaus Giger },
2253a7b2c21SNiklaus Giger {
2263a7b2c21SNiklaus Giger .mfr_id = (u16)MX_MANUFACT,
2273a7b2c21SNiklaus Giger .dev_id = MX29LV040,
2283a7b2c21SNiklaus Giger .name = "MXIC MX29LV040",
2293a7b2c21SNiklaus Giger .uaddr = {
2303a7b2c21SNiklaus Giger [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
2313a7b2c21SNiklaus Giger },
2323a7b2c21SNiklaus Giger .DevSize = SIZE_512KiB,
2333a7b2c21SNiklaus Giger .CmdSet = P_ID_AMD_STD,
2343a7b2c21SNiklaus Giger .NumEraseRegions= 1,
2353a7b2c21SNiklaus Giger .regions = {
2363a7b2c21SNiklaus Giger ERASEINFO(0x10000, 8),
2373a7b2c21SNiklaus Giger }
2383a7b2c21SNiklaus Giger },
2393a7b2c21SNiklaus Giger {
2403a7b2c21SNiklaus Giger .mfr_id = (u16)WINB_MANUFACT,
2413a7b2c21SNiklaus Giger .dev_id = W39L040A,
2423a7b2c21SNiklaus Giger .name = "WINBOND W39L040A",
2433a7b2c21SNiklaus Giger .uaddr = {
2443a7b2c21SNiklaus Giger [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
2453a7b2c21SNiklaus Giger },
2463a7b2c21SNiklaus Giger .DevSize = SIZE_512KiB,
2473a7b2c21SNiklaus Giger .CmdSet = P_ID_AMD_STD,
2483a7b2c21SNiklaus Giger .NumEraseRegions= 1,
2493a7b2c21SNiklaus Giger .regions = {
2503a7b2c21SNiklaus Giger ERASEINFO(0x10000, 8),
2513a7b2c21SNiklaus Giger }
2523a7b2c21SNiklaus Giger },
2533a7b2c21SNiklaus Giger {
2543a7b2c21SNiklaus Giger .mfr_id = (u16)AMIC_MANUFACT,
2553a7b2c21SNiklaus Giger .dev_id = A29L040,
2563a7b2c21SNiklaus Giger .name = "AMIC A29L040",
2573a7b2c21SNiklaus Giger .uaddr = {
2583a7b2c21SNiklaus Giger [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
2593a7b2c21SNiklaus Giger },
2603a7b2c21SNiklaus Giger .DevSize = SIZE_512KiB,
2613a7b2c21SNiklaus Giger .CmdSet = P_ID_AMD_STD,
2623a7b2c21SNiklaus Giger .NumEraseRegions= 1,
2633a7b2c21SNiklaus Giger .regions = {
2643a7b2c21SNiklaus Giger ERASEINFO(0x10000, 8),
2653a7b2c21SNiklaus Giger }
2663a7b2c21SNiklaus Giger },
2673a7b2c21SNiklaus Giger {
2683a7b2c21SNiklaus Giger .mfr_id = (u16)EON_MANUFACT,
2693a7b2c21SNiklaus Giger .dev_id = EN29LV040A,
2703a7b2c21SNiklaus Giger .name = "EON EN29LV040A",
2713a7b2c21SNiklaus Giger .uaddr = {
2723a7b2c21SNiklaus Giger [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
2733a7b2c21SNiklaus Giger },
2743a7b2c21SNiklaus Giger .DevSize = SIZE_512KiB,
2753a7b2c21SNiklaus Giger .CmdSet = P_ID_AMD_STD,
2763a7b2c21SNiklaus Giger .NumEraseRegions= 1,
2773a7b2c21SNiklaus Giger .regions = {
2783a7b2c21SNiklaus Giger ERASEINFO(0x10000, 8),
2793a7b2c21SNiklaus Giger }
2803a7b2c21SNiklaus Giger },
28181b20cccSMichael Schwingen #endif
2826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16
28390447ecbSTor Krill {
28428745db9SStefan Roese .mfr_id = (u16)AMD_MANUFACT,
2853b8b240dSDavid Müller .dev_id = AM29F400BB,
2863b8b240dSDavid Müller .name = "AMD AM29F400BB",
2873b8b240dSDavid Müller .uaddr = {
2883b8b240dSDavid Müller [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
2893b8b240dSDavid Müller },
2903b8b240dSDavid Müller .DevSize = SIZE_512KiB,
2913b8b240dSDavid Müller .CmdSet = CFI_CMDSET_AMD_LEGACY,
2923b8b240dSDavid Müller .NumEraseRegions= 4,
2933b8b240dSDavid Müller .regions = {
2943b8b240dSDavid Müller ERASEINFO(0x04000, 1),
2953b8b240dSDavid Müller ERASEINFO(0x02000, 2),
2963b8b240dSDavid Müller ERASEINFO(0x08000, 1),
2973b8b240dSDavid Müller ERASEINFO(0x10000, 7),
2983b8b240dSDavid Müller }
2993b8b240dSDavid Müller },
3003b8b240dSDavid Müller {
3013b8b240dSDavid Müller .mfr_id = (u16)AMD_MANUFACT,
30290447ecbSTor Krill .dev_id = AM29LV400BB,
30390447ecbSTor Krill .name = "AMD AM29LV400BB",
30490447ecbSTor Krill .uaddr = {
30590447ecbSTor Krill [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
30690447ecbSTor Krill },
30790447ecbSTor Krill .DevSize = SIZE_512KiB,
30890447ecbSTor Krill .CmdSet = CFI_CMDSET_AMD_LEGACY,
30990447ecbSTor Krill .NumEraseRegions= 4,
31090447ecbSTor Krill .regions = {
31190447ecbSTor Krill ERASEINFO(0x04000,1),
31290447ecbSTor Krill ERASEINFO(0x02000,2),
31390447ecbSTor Krill ERASEINFO(0x08000,1),
31490447ecbSTor Krill ERASEINFO(0x10000,7),
31590447ecbSTor Krill }
31690447ecbSTor Krill },
3177949839eSGuennadi Liakhovetski {
31828745db9SStefan Roese .mfr_id = (u16)AMD_MANUFACT,
3197949839eSGuennadi Liakhovetski .dev_id = AM29LV800BB,
3207949839eSGuennadi Liakhovetski .name = "AMD AM29LV800BB",
3217949839eSGuennadi Liakhovetski .uaddr = {
3227949839eSGuennadi Liakhovetski [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
3237949839eSGuennadi Liakhovetski },
3247949839eSGuennadi Liakhovetski .DevSize = SIZE_1MiB,
3257949839eSGuennadi Liakhovetski .CmdSet = CFI_CMDSET_AMD_LEGACY,
3267949839eSGuennadi Liakhovetski .NumEraseRegions= 4,
3277949839eSGuennadi Liakhovetski .regions = {
3287949839eSGuennadi Liakhovetski ERASEINFO(0x04000, 1),
3297949839eSGuennadi Liakhovetski ERASEINFO(0x02000, 2),
3307949839eSGuennadi Liakhovetski ERASEINFO(0x08000, 1),
3317949839eSGuennadi Liakhovetski ERASEINFO(0x10000, 15),
3327949839eSGuennadi Liakhovetski }
3337949839eSGuennadi Liakhovetski },
3345e72ef08SDavid Müller (ELSOFT AG) {
335f3c89d92SDirk Eibach .mfr_id = (u16)AMD_MANUFACT,
336f3c89d92SDirk Eibach .dev_id = AM29LV800BT,
337f3c89d92SDirk Eibach .name = "AMD AM29LV800BT",
338f3c89d92SDirk Eibach .uaddr = {
339f3c89d92SDirk Eibach [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
340f3c89d92SDirk Eibach },
341f3c89d92SDirk Eibach .DevSize = SIZE_1MiB,
342f3c89d92SDirk Eibach .CmdSet = CFI_CMDSET_AMD_LEGACY,
343f3c89d92SDirk Eibach .NumEraseRegions= 4,
344f3c89d92SDirk Eibach .regions = {
345f3c89d92SDirk Eibach ERASEINFO(0x10000, 15),
346f3c89d92SDirk Eibach ERASEINFO(0x08000, 1),
347f3c89d92SDirk Eibach ERASEINFO(0x02000, 2),
348f3c89d92SDirk Eibach ERASEINFO(0x04000, 1),
349f3c89d92SDirk Eibach }
350f3c89d92SDirk Eibach },
351f3c89d92SDirk Eibach {
352f3c89d92SDirk Eibach .mfr_id = (u16)MX_MANUFACT,
353f3c89d92SDirk Eibach .dev_id = AM29LV800BT,
354f3c89d92SDirk Eibach .name = "MXIC MX29LV800BT",
355f3c89d92SDirk Eibach .uaddr = {
356f3c89d92SDirk Eibach [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
357f3c89d92SDirk Eibach },
358f3c89d92SDirk Eibach .DevSize = SIZE_1MiB,
359f3c89d92SDirk Eibach .CmdSet = CFI_CMDSET_AMD_LEGACY,
360f3c89d92SDirk Eibach .NumEraseRegions= 4,
361f3c89d92SDirk Eibach .regions = {
362f3c89d92SDirk Eibach ERASEINFO(0x10000, 15),
363f3c89d92SDirk Eibach ERASEINFO(0x08000, 1),
364f3c89d92SDirk Eibach ERASEINFO(0x02000, 2),
365f3c89d92SDirk Eibach ERASEINFO(0x04000, 1),
366f3c89d92SDirk Eibach }
367f3c89d92SDirk Eibach },
368f3c89d92SDirk Eibach {
369f3c89d92SDirk Eibach .mfr_id = (u16)EON_ALT_MANU,
370f3c89d92SDirk Eibach .dev_id = AM29LV800BT,
371f3c89d92SDirk Eibach .name = "EON EN29LV800BT",
372f3c89d92SDirk Eibach .uaddr = {
373f3c89d92SDirk Eibach [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
374f3c89d92SDirk Eibach },
375f3c89d92SDirk Eibach .DevSize = SIZE_1MiB,
376f3c89d92SDirk Eibach .CmdSet = CFI_CMDSET_AMD_LEGACY,
377f3c89d92SDirk Eibach .NumEraseRegions= 4,
378f3c89d92SDirk Eibach .regions = {
379f3c89d92SDirk Eibach ERASEINFO(0x10000, 15),
380f3c89d92SDirk Eibach ERASEINFO(0x08000, 1),
381f3c89d92SDirk Eibach ERASEINFO(0x02000, 2),
382f3c89d92SDirk Eibach ERASEINFO(0x04000, 1),
383f3c89d92SDirk Eibach }
384f3c89d92SDirk Eibach },
385f3c89d92SDirk Eibach {
3865e72ef08SDavid Müller (ELSOFT AG) .mfr_id = (u16)STM_MANUFACT,
3875e72ef08SDavid Müller (ELSOFT AG) .dev_id = STM29F400BB,
3885e72ef08SDavid Müller (ELSOFT AG) .name = "ST Micro M29F400BB",
3895e72ef08SDavid Müller (ELSOFT AG) .uaddr = {
3905e72ef08SDavid Müller (ELSOFT AG) [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
3915e72ef08SDavid Müller (ELSOFT AG) },
3925e72ef08SDavid Müller (ELSOFT AG) .DevSize = SIZE_512KiB,
3935e72ef08SDavid Müller (ELSOFT AG) .CmdSet = CFI_CMDSET_AMD_LEGACY,
3945e72ef08SDavid Müller (ELSOFT AG) .NumEraseRegions = 4,
3955e72ef08SDavid Müller (ELSOFT AG) .regions = {
3965e72ef08SDavid Müller (ELSOFT AG) ERASEINFO(0x04000, 1),
3975e72ef08SDavid Müller (ELSOFT AG) ERASEINFO(0x02000, 2),
3985e72ef08SDavid Müller (ELSOFT AG) ERASEINFO(0x08000, 1),
3995e72ef08SDavid Müller (ELSOFT AG) ERASEINFO(0x10000, 7),
4005e72ef08SDavid Müller (ELSOFT AG) }
4015e72ef08SDavid Müller (ELSOFT AG) },
40290447ecbSTor Krill #endif
40381b20cccSMichael Schwingen };
40481b20cccSMichael Schwingen
fill_info(flash_info_t * info,const struct amd_flash_info * jedec_entry,ulong base)40581b20cccSMichael Schwingen static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
40681b20cccSMichael Schwingen {
40781b20cccSMichael Schwingen int i,j;
40881b20cccSMichael Schwingen int sect_cnt;
40981b20cccSMichael Schwingen int size_ratio;
41081b20cccSMichael Schwingen int total_size;
41181b20cccSMichael Schwingen enum uaddr uaddr_idx;
41281b20cccSMichael Schwingen
41381b20cccSMichael Schwingen size_ratio = info->portwidth / info->chipwidth;
41481b20cccSMichael Schwingen
41581b20cccSMichael Schwingen debug("Found JEDEC Flash: %s\n", jedec_entry->name);
41681b20cccSMichael Schwingen info->vendor = jedec_entry->CmdSet;
41781b20cccSMichael Schwingen /* Todo: do we need device-specific timeouts? */
41881b20cccSMichael Schwingen info->erase_blk_tout = 30000;
41981b20cccSMichael Schwingen info->buffer_write_tout = 1000;
42081b20cccSMichael Schwingen info->write_tout = 100;
42181b20cccSMichael Schwingen info->name = jedec_entry->name;
42281b20cccSMichael Schwingen
42381b20cccSMichael Schwingen /* copy unlock addresses from device table to CFI info struct. This
42481b20cccSMichael Schwingen is just here because the addresses are in the table anyway - if
42581b20cccSMichael Schwingen the flash is not detected due to wrong unlock addresses,
42681b20cccSMichael Schwingen flash_detect_legacy would have to try all of them before we even
42781b20cccSMichael Schwingen get here. */
42881b20cccSMichael Schwingen switch(info->chipwidth) {
42981b20cccSMichael Schwingen case FLASH_CFI_8BIT:
43081b20cccSMichael Schwingen uaddr_idx = jedec_entry->uaddr[0];
43181b20cccSMichael Schwingen break;
43281b20cccSMichael Schwingen case FLASH_CFI_16BIT:
43381b20cccSMichael Schwingen uaddr_idx = jedec_entry->uaddr[1];
43481b20cccSMichael Schwingen break;
43581b20cccSMichael Schwingen case FLASH_CFI_32BIT:
43681b20cccSMichael Schwingen uaddr_idx = jedec_entry->uaddr[2];
43781b20cccSMichael Schwingen break;
43881b20cccSMichael Schwingen default:
43981b20cccSMichael Schwingen uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
44081b20cccSMichael Schwingen break;
44181b20cccSMichael Schwingen }
44281b20cccSMichael Schwingen
44381b20cccSMichael Schwingen debug("unlock address index %d\n", uaddr_idx);
44481b20cccSMichael Schwingen info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
44581b20cccSMichael Schwingen info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
446f382b7c5SMarek Vasut debug("unlock addresses are 0x%lx/0x%lx\n",
447f382b7c5SMarek Vasut info->addr_unlock1, info->addr_unlock2);
44881b20cccSMichael Schwingen
44981b20cccSMichael Schwingen sect_cnt = 0;
45081b20cccSMichael Schwingen total_size = 0;
45181b20cccSMichael Schwingen for (i = 0; i < jedec_entry->NumEraseRegions; i++) {
45281b20cccSMichael Schwingen ulong erase_region_size = jedec_entry->regions[i] >> 8;
45381b20cccSMichael Schwingen ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1;
45481b20cccSMichael Schwingen
45581b20cccSMichael Schwingen total_size += erase_region_size * erase_region_count;
456f382b7c5SMarek Vasut debug("erase_region_count = %ld erase_region_size = %ld\n",
45781b20cccSMichael Schwingen erase_region_count, erase_region_size);
45881b20cccSMichael Schwingen for (j = 0; j < erase_region_count; j++) {
4596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
46081b20cccSMichael Schwingen printf("ERROR: too many flash sectors\n");
46181b20cccSMichael Schwingen break;
46281b20cccSMichael Schwingen }
46381b20cccSMichael Schwingen info->start[sect_cnt] = base;
46481b20cccSMichael Schwingen base += (erase_region_size * size_ratio);
46581b20cccSMichael Schwingen sect_cnt++;
46681b20cccSMichael Schwingen }
46781b20cccSMichael Schwingen }
46881b20cccSMichael Schwingen info->sector_count = sect_cnt;
46981b20cccSMichael Schwingen info->size = total_size * size_ratio;
47081b20cccSMichael Schwingen }
47181b20cccSMichael Schwingen
47281b20cccSMichael Schwingen /*-----------------------------------------------------------------------
47381b20cccSMichael Schwingen * match jedec ids against table. If a match is found, fill flash_info entry
47481b20cccSMichael Schwingen */
jedec_flash_match(flash_info_t * info,ulong base)47581b20cccSMichael Schwingen int jedec_flash_match(flash_info_t *info, ulong base)
47681b20cccSMichael Schwingen {
47781b20cccSMichael Schwingen int ret = 0;
47881b20cccSMichael Schwingen int i;
47981b20cccSMichael Schwingen ulong mask = 0xFFFF;
48081b20cccSMichael Schwingen if (info->chipwidth == 1)
48181b20cccSMichael Schwingen mask = 0xFF;
48281b20cccSMichael Schwingen
48381b20cccSMichael Schwingen for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
48481b20cccSMichael Schwingen if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) &&
48581b20cccSMichael Schwingen (jedec_table[i].dev_id & mask) == (info->device_id & mask)) {
48681b20cccSMichael Schwingen fill_info(info, &jedec_table[i], base);
48781b20cccSMichael Schwingen ret = 1;
48881b20cccSMichael Schwingen break;
48981b20cccSMichael Schwingen }
49081b20cccSMichael Schwingen }
49181b20cccSMichael Schwingen return ret;
49281b20cccSMichael Schwingen }
493