Lines Matching +full:0 +full:x02000
16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
28 #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
29 #define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
30 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
31 #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
32 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
33 #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
34 #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
35 #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
37 #define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
38 #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
39 #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
42 #define TITAN_REGS_ESWITCH_BASE (0x08640000)
44 #define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
45 #define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
46 #define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
47 #define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
49 #define AR7_RESET_PERIPHERAL 0x0
50 #define AR7_RESET_SOFTWARE 0x4
51 #define AR7_RESET_STATUS 0x8
61 #define AR7_GPIO_INPUT 0x0
62 #define AR7_GPIO_OUTPUT 0x4
63 #define AR7_GPIO_DIR 0x8
64 #define AR7_GPIO_ENABLE 0xc
65 #define TITAN_GPIO_INPUT_0 0x0
66 #define TITAN_GPIO_INPUT_1 0x4
67 #define TITAN_GPIO_OUTPUT_0 0x8
68 #define TITAN_GPIO_OUTPUT_1 0xc
69 #define TITAN_GPIO_DIR_0 0x10
70 #define TITAN_GPIO_DIR_1 0x14
71 #define TITAN_GPIO_ENBL_0 0x18
72 #define TITAN_GPIO_ENBL_1 0x1c
74 #define AR7_CHIP_7100 0x18
75 #define AR7_CHIP_7200 0x2b
76 #define AR7_CHIP_7300 0x05
77 #define AR7_CHIP_TITAN 0x07
78 #define TITAN_CHIP_1050 0x0f
79 #define TITAN_CHIP_1055 0x0e
80 #define TITAN_CHIP_1056 0x0d
81 #define TITAN_CHIP_1060 0x07
93 #define AR7_WDT_HW_ENA 0x10
109 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == in ar7_is_titan()
116 KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff); in ar7_chip_id()
123 return ((val >> 12) & 0x0f); in titan_chip_id()
128 return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : in ar7_chip_rev()
129 0x14))) >> 16) & 0xff; in ar7_chip_rev()
138 return 0; in ar7_has_high_cpmac()