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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
H A Ddra7.dtsi61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
109 opp-supported-hw = <0xFF 0x01>;
119 opp-supported-hw = <0xFF 0x02>;
[all …]
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
/openbmc/u-boot/include/configs/
H A Dax25-ae350.h43 #define CONFIG_SYS_FDT_BASE 0x000f0000
48 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
51 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
52 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
65 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
72 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
93 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */
109 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
112 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
116 #define CONFIG_ENV_SECT_SIZE 0x1000
[all …]
H A Drk3328_common.h17 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
18 #define CONFIG_SYS_LOAD_ADDR 0x00800800
26 #define CONFIG_SYS_SDRAM_BASE 0
27 #define SDRAM_MAX_SIZE 0xff000000
32 "scriptaddr=0x00500000\0" \
33 "pxefile_addr_r=0x00600000\0" \
34 "fdt_addr_r=0x01f00000\0" \
35 "kernel_addr_r=0x02080000\0" \
36 "ramdisk_addr_r=0x04000000\0"
41 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
H A Drk3399_common.h19 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000
20 #define CONFIG_SYS_LOAD_ADDR 0x00800800
21 #define CONFIG_SPL_STACK 0xff8effff
22 #define CONFIG_SPL_TEXT_BASE 0xff8c2000
23 #define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000
25 #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
26 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000
38 #define CONFIG_SYS_SDRAM_BASE 0
39 #define SDRAM_MAX_SIZE 0xf8000000
44 "scriptaddr=0x00500000\0" \
[all …]
H A Drk3288_common.h17 #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
21 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
23 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000
24 #define CONFIG_SYS_LOAD_ADDR 0x00800800
25 #define CONFIG_SPL_STACK 0xff718000
27 # define CONFIG_SPL_TEXT_BASE 0x0
29 # define CONFIG_SPL_TEXT_BASE 0xff704000
39 #define CONFIG_SYS_SDRAM_BASE 0
41 #define SDRAM_MAX_SIZE 0xfe000000
51 "scriptaddr=0x00000000\0" \
[all …]
H A Domap3_pandora.h33 "if mmc rescan && load mmc 0:1 ${loadaddr} autoboot.scr; then " \
40 func(MMC, mmc, 0) \
46 "usbtty=cdc_acm\0" \
48 "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
49 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
55 0x01F00000) /* 31MB */
66 #define CONFIG_ENV_OFFSET 0x260000
67 #define CONFIG_ENV_ADDR 0x260000
H A Domap3_zoom1.h36 #define CONFIG_USBD_VENDORID 0x0451
37 #define CONFIG_USBD_PRODUCTID 0x5678
44 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
62 "loadaddr=0x82000000\0" \
63 "fdtaddr=0x80f80000\0" \
64 "bootfile=uImage\0" \
65 "fdtfile=omap3-ldp.dtb\0" \
66 "bootdir=/\0" \
67 "bootpart=0:1\0" \
68 "usbtty=cdc_acm\0" \
[all …]
H A Dam3517_evm.h73 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
74 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
77 * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000
78 * U-Boot 15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000
79 * U-Boot environment 2 * NAND_BLOCK_SIZE = 256 KiB @ 0x260000
80 * Kernel 64 * NAND_BLOCK_SIZE = 8 MiB @ 0x2A0000
81 * DTB 4 * NAND_BLOCK_SIZE = 512 KiB @ 0xAA0000
82 * RootFS Remaining Flash Space @ 0xB20000
91 "loadaddr=0x82000000\0" \
92 "console=ttyS2,115200n8\0" \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-support-card.dtsi10 ranges = <1 0x00000000 0x42000000 0x02000000>;
14 reg = <1 0x01f00000 0x1000>;
22 reg = <1 0x01fb0000 0x20>;
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A D82571.h7 #define ID_LED_RESERVED_F746 0xF746
13 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
17 #define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n)))
19 #define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
20 #define E1000_EIAC_MASK_82574 0x01F00000
22 #define E1000_IVAR_INT_ALLOC_VALID 0x8
25 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000
28 #define E1000_IDLE_ERROR_COUNT_MASK 0xFF
30 #define E1000_RECEIVE_ERROR_MAX 0xFFFF
/openbmc/u-boot/arch/arm/dts/
H A Duniphier-support-card.dtsi10 ranges = <1 0x00000000 0x42000000 0x02000000>;
16 ranges = <0x00000000 1 0x01f00000 0x00100000>;
19 ethsc: ethernet@0 {
21 reg = <0x00000000 0x1000>;
28 reg = <0x000b0000 0x20>;
H A Ddra7.dtsi59 reg = <0x0 0x48211000 0x0 0x1000>,
60 <0x0 0x48212000 0x0 0x2000>,
61 <0x0 0x48214000 0x0 0x2000>,
62 <0x0 0x48216000 0x0 0x2000>;
71 reg = <0x0 0x48281000 0x0 0x1000>;
77 #size-cells = <0>;
79 cpu0: cpu@0 {
82 reg = <0>;
92 cooling-min-level = <0>;
105 opp-supported-hw = <0xFF 0x01>;
[all …]
/openbmc/linux/arch/sh/configs/
H A Dul2_defconfig12 CONFIG_MEMORY_SIZE=0x01f00000
/openbmc/linux/arch/powerpc/boot/dts/
H A Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
H A Dlite5200b.dts22 gpios = <&gpt2 0 1>;
25 gpios = <&gpt3 0 1>;
34 memory@0 {
35 reg = <0x00000000 0x10000000>; // 256MB
41 cell-index = <0>;
87 phy0: ethernet-phy@0 {
88 reg = <0>;
95 reg = <0x50>;
101 reg = <0x8000 0x4000>;
106 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
H A Diss4xx-mpic.dts17 /memreserve/ 0x01f00000 0x00100000;
24 dcr-parent = <&{/cpus/cpu@0}>;
32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
62 cpu-release-addr = <0 0x01f00100>;
78 cpu-release-addr = <0 0x01f00200>;
94 cpu-release-addr = <0 0x01f00300>;
100 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
107 dcr-reg = <0xffc00000 0x00030000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dallwinner,sun6i-a31-rtc.yaml42 - description: RTC Alarm 0
58 - the Low Frequency Oscillator or LOSC, at index 0,
188 reg = <0x01f00000 0x400>;
189 interrupts = <0 40 4>, <0 41 4>;
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1020utm-pc.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x2000000>;
44 partition@0 {
46 reg = <0x0 0x00040000>;
52 reg = <0x00040000 0x003c0000>;
58 reg = <0x00400000 0x01b00000>;
66 reg = <0x01f00000 0x00100000>;
77 reg = <0x68>;
82 phy0: ethernet-phy@0 {
83 interrupts = <3 1 0 0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h11 #define SUNXI_SRAM_A1_BASE 0x00000000
14 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20 #define SUNXI_DE2_BASE 0x01000000
23 #define SUNXI_CPUCFG_BASE 0x01700000
26 #define SUNXI_SRAMC_BASE 0x01c00000
27 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dfsl,imx6q-pcie.yaml167 reg = <0x01ffc000 0x04000>,
168 <0x01f00000 0x80000>;
173 bus-range = <0x00 0xff>;
174 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
175 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
180 interrupt-map-mask = <0 0 0 0x7>;
181 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
184 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dmicro-support-card.c14 #define MICRO_SUPPORT_CARD_BASE 0x43f00000
15 #define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
16 #define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000)
17 #define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
18 #define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
19 #define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
22 * 0: reset deassert, 1: reset
24 * bit[0]: LAN, I2C, LED
29 writel(0x00010000, MICRO_SUPPORT_CARD_RESET); in support_card_reset_deassert()
34 writel(0x00020003, MICRO_SUPPORT_CARD_RESET); in support_card_reset()
[all …]

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