1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 251dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3f25701dfSBruce Allan 4f25701dfSBruce Allan #ifndef _E1000E_82571_H_ 5f25701dfSBruce Allan #define _E1000E_82571_H_ 6f25701dfSBruce Allan 7f25701dfSBruce Allan #define ID_LED_RESERVED_F746 0xF746 8f25701dfSBruce Allan #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ 9f25701dfSBruce Allan (ID_LED_OFF1_ON2 << 8) | \ 10f25701dfSBruce Allan (ID_LED_DEF1_DEF2 << 4) | \ 11f25701dfSBruce Allan (ID_LED_DEF1_DEF2)) 12f25701dfSBruce Allan 13f25701dfSBruce Allan #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 14f25701dfSBruce Allan #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */ 15f25701dfSBruce Allan 16f25701dfSBruce Allan /* Intr Throttling - RW */ 17f25701dfSBruce Allan #define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n))) 18f25701dfSBruce Allan 19f25701dfSBruce Allan #define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */ 20f25701dfSBruce Allan #define E1000_EIAC_MASK_82574 0x01F00000 21f25701dfSBruce Allan 223ffcf2cbSBruce Allan #define E1000_IVAR_INT_ALLOC_VALID 0x8 233ffcf2cbSBruce Allan 24f25701dfSBruce Allan /* Manageability Operation Mode mask */ 25f25701dfSBruce Allan #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 26f25701dfSBruce Allan 27f25701dfSBruce Allan #define E1000_BASE1000T_STATUS 10 28f25701dfSBruce Allan #define E1000_IDLE_ERROR_COUNT_MASK 0xFF 29f25701dfSBruce Allan #define E1000_RECEIVE_ERROR_COUNTER 21 30f25701dfSBruce Allan #define E1000_RECEIVE_ERROR_MAX 0xFFFF 31f25701dfSBruce Allan bool e1000_check_phy_82574(struct e1000_hw *hw); 32f25701dfSBruce Allan bool e1000e_get_laa_state_82571(struct e1000_hw *hw); 33f25701dfSBruce Allan void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); 34f25701dfSBruce Allan 35f25701dfSBruce Allan #endif 36