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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h11 #define SUNXI_SRAM_A1_BASE 0x00000000
14 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20 #define SUNXI_DE2_BASE 0x01000000
23 #define SUNXI_CPUCFG_BASE 0x01700000
26 #define SUNXI_SRAMC_BASE 0x01c00000
27 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
38 #define DAVINCI_UART0_BASE (0x01c20000)
39 #define DAVINCI_UART1_BASE (0x01c20400)
40 #define DAVINCI_TIMER3_BASE (0x01c20800)
41 #define DAVINCI_I2C_BASE (0x01c21000)
42 #define DAVINCI_TIMER0_BASE (0x01c21400)
43 #define DAVINCI_TIMER1_BASE (0x01c21800)
44 #define DAVINCI_WDOG_BASE (0x01c21c00)
[all …]
H A Dda8xx-usb.h18 #define DA8XX_USB_OTG_BASE 0x01E00000
21 #define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
24 #define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
53 #define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
54 #define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
55 #define DA8XX_USB_TXINT_SHIFT 0
58 #define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
69 #define CFGCHIP2_NO_OVERRIDE (0 << 13)
82 #define CFGCHIP2_REFFREQ (0xf << 0)
83 #define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/openbmc/u-boot/include/
H A Dfsl_qe.h20 #define QE_DATAONLY_BASE 0
37 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
38 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
39 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
40 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
50 #define QE_CR_FLG 0x00010000
51 #define QE_RESET 0x80000000
52 #define QE_INIT_TX_RX 0x00000000
53 #define QE_INIT_RX 0x00000001
54 #define QE_INIT_TX 0x00000002
[all …]
H A Dlcdvideo.h11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi13 reg = <0 0xfc000000 0 0x1000>;
20 ports-implemented = <0x1>;
27 reg = <0x0 0xfdc70000 0x0 0x1000>;
32 reg = <0x0 0xfe190080 0x0 0x20>;
37 reg = <0x0 0xfe190100 0x0 0x20>;
42 reg = <0x0 0xfe190200 0x0 0x20>;
47 reg = <0x0 0xfdcb8000 0x0 0x10000>;
52 reg = <0x0 0xfe8c0000 0x0 0x20000>;
53 #phy-cells = <0>;
67 bus-range = <0x0 0xf>;
[all …]
/openbmc/u-boot/include/configs/
H A Dmeesc.h58 #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
59 #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
64 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
65 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
66 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
79 # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
94 #define CONFIG_ET1100_BASE 0x70000000
99 #define CONFIG_ENV_OFFSET 0x4200
100 #define CONFIG_ENV_SIZE 0x4200
101 #define CONFIG_ENV_SECT_SIZE 0x210
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-frontend.yaml63 port@0:
94 reg = <0x01e00000 0x20000>;
104 #size-cells = <0>;
108 #size-cells = <0>;
111 fe0_out_be0: endpoint@0 {
112 reg = <0>;
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62p5-sk.dts29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
30 <0x00000008 0x80000000 0x00000001 0x80000000>;
40 reg = <0x00 0x9e780000 0x00 0x80000>;
45 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
51 reg = <0x00 0x9c900000 0x00 0x01e00000>;
61 AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
62 AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
63 AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */
64 AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */
71 AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */
[all …]
H A Dk3-am62a7-sk.dts33 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
34 <0x00000008 0x80000000 0x00000000 0x80000000>;
43 reg = <0x00 0x9e780000 0x00 0x80000>;
44 alignment = <0x1000>;
49 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
50 alignment = <0x1000>;
56 reg = <0x00 0x9c900000 0x00 0x01e00000>;
61 vmain_pd: regulator-0 {
107 pinctrl-0 = <&usr_led_pins_default>;
109 led-0 {
[all …]
/openbmc/linux/arch/nios2/boot/dts/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dgk104.c35 for (i = 0; i < 64; i++) { in gk104_top_parse()
39 type = ~0; in gk104_top_parse()
40 inst = 0; in gk104_top_parse()
43 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_parse()
45 switch (data & 0x00000003) { in gk104_top_parse()
46 case 0x00000000: /* NOT_VALID */ in gk104_top_parse()
48 case 0x00000001: /* DATA */ in gk104_top_parse()
49 inst = (data & 0x3c000000) >> 26; in gk104_top_parse()
50 info->addr = (data & 0x00fff000); in gk104_top_parse()
51 if (data & 0x00000004) in gk104_top_parse()
[all …]
/openbmc/u-boot/arch/nios2/dts/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0x0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dts72xx.c70 #define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */
71 #define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */
82 bits = __raw_readb(addr) & ~0x07; in ts72xx_nand_hwcontrol()
83 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ in ts72xx_nand_hwcontrol()
85 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ in ts72xx_nand_hwcontrol()
100 return !!(__raw_readb(addr) & 0x20); in ts72xx_nand_device_ready()
109 .offset = 0,
128 .chip_offset = 0,
139 .start = 0, /* filled in later */
140 .end = 0, /* filled in later */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5800-peach-pi.dts34 pwms = <&pwm 0 1000000 0>;
35 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
78 reg = <0x9>;
89 sound-dai = <&i2s0 0>;
93 sound-dai = <&max98090 0>;
100 reg = <0x10>;
114 reg = <0x20>;
120 firmware_storage_spi: flash@0 {
121 reg = <0>;
127 elog-panic-event-offset = <0x01e00000 0x100000>;
[all …]
H A Dexynos5420-peach-pit.dts35 pwms = <&pwm 0 1000000 0>;
36 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
66 reg = <0x9>;
77 sound-dai = <&i2s0 0>;
81 sound-dai = <&max98090 0>;
88 reg = <0x10>;
95 reg = <0x48>;
99 0x02 0xa1 0x01 /* HPD low */
102 * [1:0] SW output 1.2V voltage is lower to 96%
104 0x04 0x14 0x01
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h14 u32 chipid; /* 0x0 */
20 u32 otpstatus; /* 0x10, corerev >= 10 */
26 u32 intstatus; /* 0x20 */
30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
40 u32 flashcontrol; /* 0x40 */
46 u32 broadcastaddress; /* 0x50 */
50 u32 gpiopullup; /* 0x58, corerev >= 20 */
51 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
[all …]
/openbmc/linux/include/soc/fsl/qe/
H A Dqe.h32 QE_CLK_NONE = 0,
131 return 0; in cpm_muram_dma()
227 return 0; in qe_alive_during_sleep()
271 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
284 __be32 traps[16]; /* Trap addresses, 0 == ignore */
328 #define BD_STATUS_MASK 0xffff0000
329 #define BD_LENGTH_MASK 0x0000ffff
337 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
338 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
339 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h22 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
29 u32 dram_timing4; /* 0x10 */
34 u32 dram_addrw; /* 0x2c */
35 u32 dram_if_width; /* 0x30 */
39 u32 sbe_count; /* 0x40 */
43 u32 drop_addr; /* 0x50 */
47 u32 ctrl_width; /* 0x60 */
51 u32 rfifo_cmap; /* 0x70 */
55 u32 fpgaport_rst; /* 0x80 */
59 u32 prot_rule_addr; /* 0x90 */
[all …]
/openbmc/linux/arch/mips/include/asm/mips-boards/
H A Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_int_process_v11.c40 * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus
44 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
49 * - context_id0[24:0]
51 * Auto - only context_id0[8:0] is used, which reports various interrupts
52 * generated by SQG. The rest is 0.
53 * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0])
54 * Error - Error Type (context_id0[24:21]), Error Details (context_id0[20:0])
57 * S_SENDMSG and Errors. These are 0 for Auto.
61 SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0,
67 SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0,
[all …]

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