1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 23d357619SMasahiro Yamada /* 33d357619SMasahiro Yamada * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions. 43d357619SMasahiro Yamada * 53d357619SMasahiro Yamada * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> 63d357619SMasahiro Yamada * 73d357619SMasahiro Yamada * Based on drivers/usb/musb/davinci.h 83d357619SMasahiro Yamada * 93d357619SMasahiro Yamada * Copyright (C) 2009 Texas Instruments Incorporated 103d357619SMasahiro Yamada */ 113d357619SMasahiro Yamada #ifndef __DA8XX_MUSB_H__ 123d357619SMasahiro Yamada #define __DA8XX_MUSB_H__ 133d357619SMasahiro Yamada 143d357619SMasahiro Yamada #include <asm/arch/hardware.h> 153d357619SMasahiro Yamada #include <asm/arch/gpio.h> 163d357619SMasahiro Yamada 173d357619SMasahiro Yamada /* Base address of da8xx usb0 wrapper */ 183d357619SMasahiro Yamada #define DA8XX_USB_OTG_BASE 0x01E00000 193d357619SMasahiro Yamada 203d357619SMasahiro Yamada /* Base address of da8xx musb core */ 213d357619SMasahiro Yamada #define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400) 223d357619SMasahiro Yamada 233d357619SMasahiro Yamada /* Timeout for DA8xx usb module */ 243d357619SMasahiro Yamada #define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF 253d357619SMasahiro Yamada 263d357619SMasahiro Yamada /* 273d357619SMasahiro Yamada * DA8xx platform USB wrapper register overlay. 283d357619SMasahiro Yamada */ 293d357619SMasahiro Yamada struct da8xx_usb_regs { 303d357619SMasahiro Yamada dv_reg revision; 313d357619SMasahiro Yamada dv_reg control; 323d357619SMasahiro Yamada dv_reg status; 333d357619SMasahiro Yamada dv_reg emulation; 343d357619SMasahiro Yamada dv_reg mode; 353d357619SMasahiro Yamada dv_reg autoreq; 363d357619SMasahiro Yamada dv_reg srpfixtime; 373d357619SMasahiro Yamada dv_reg teardown; 383d357619SMasahiro Yamada dv_reg intsrc; 393d357619SMasahiro Yamada dv_reg intsrc_set; 403d357619SMasahiro Yamada dv_reg intsrc_clr; 413d357619SMasahiro Yamada dv_reg intmsk; 423d357619SMasahiro Yamada dv_reg intmsk_set; 433d357619SMasahiro Yamada dv_reg intmsk_clr; 443d357619SMasahiro Yamada dv_reg intsrcmsk; 453d357619SMasahiro Yamada dv_reg eoi; 463d357619SMasahiro Yamada dv_reg intvector; 473d357619SMasahiro Yamada dv_reg grndis_size[4]; 483d357619SMasahiro Yamada }; 493d357619SMasahiro Yamada 503d357619SMasahiro Yamada #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE) 513d357619SMasahiro Yamada 523d357619SMasahiro Yamada /* DA8XX interrupt bits definitions */ 533d357619SMasahiro Yamada #define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ 543d357619SMasahiro Yamada #define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ 553d357619SMasahiro Yamada #define DA8XX_USB_TXINT_SHIFT 0 563d357619SMasahiro Yamada #define DA8XX_USB_RXINT_SHIFT 8 573d357619SMasahiro Yamada 583d357619SMasahiro Yamada #define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ 593d357619SMasahiro Yamada #define DA8XX_USB_TXINT_MASK \ 603d357619SMasahiro Yamada (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT) 613d357619SMasahiro Yamada #define DA8XX_USB_RXINT_MASK \ 623d357619SMasahiro Yamada (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT) 633d357619SMasahiro Yamada 643d357619SMasahiro Yamada /* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ 653d357619SMasahiro Yamada #define CFGCHIP2_PHYCLKGD (1 << 17) 663d357619SMasahiro Yamada #define CFGCHIP2_VBUSSENSE (1 << 16) 673d357619SMasahiro Yamada #define CFGCHIP2_RESET (1 << 15) 683d357619SMasahiro Yamada #define CFGCHIP2_OTGMODE (3 << 13) 693d357619SMasahiro Yamada #define CFGCHIP2_NO_OVERRIDE (0 << 13) 703d357619SMasahiro Yamada #define CFGCHIP2_FORCE_HOST (1 << 13) 713d357619SMasahiro Yamada #define CFGCHIP2_FORCE_DEVICE (2 << 13) 723d357619SMasahiro Yamada #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) 733d357619SMasahiro Yamada #define CFGCHIP2_USB1PHYCLKMUX (1 << 12) 743d357619SMasahiro Yamada #define CFGCHIP2_USB2PHYCLKMUX (1 << 11) 753d357619SMasahiro Yamada #define CFGCHIP2_PHYPWRDN (1 << 10) 763d357619SMasahiro Yamada #define CFGCHIP2_OTGPWRDN (1 << 9) 773d357619SMasahiro Yamada #define CFGCHIP2_DATPOL (1 << 8) 783d357619SMasahiro Yamada #define CFGCHIP2_USB1SUSPENDM (1 << 7) 793d357619SMasahiro Yamada #define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ 803d357619SMasahiro Yamada #define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ 813d357619SMasahiro Yamada #define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ 823d357619SMasahiro Yamada #define CFGCHIP2_REFFREQ (0xf << 0) 833d357619SMasahiro Yamada #define CFGCHIP2_REFFREQ_12MHZ (1 << 0) 843d357619SMasahiro Yamada #define CFGCHIP2_REFFREQ_24MHZ (2 << 0) 853d357619SMasahiro Yamada #define CFGCHIP2_REFFREQ_48MHZ (3 << 0) 863d357619SMasahiro Yamada 873d357619SMasahiro Yamada #define DA8XX_USB_VBUS_GPIO (1 << 15) 883d357619SMasahiro Yamada 893d357619SMasahiro Yamada int usb_phy_on(void); 903d357619SMasahiro Yamada void usb_phy_off(void); 913d357619SMasahiro Yamada 923d357619SMasahiro Yamada #endif /* __DA8XX_MUSB_H__ */ 93