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/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/openbmc/linux/drivers/video/fbdev/riva/
H A Driva_tbl.h55 {0x00000050, 0x00000000},
56 {0x00000080, 0xFFFF00FF},
57 {0x00000080, 0xFFFFFFFF}
61 {0x00000080, 0x00000008},
62 {0x00000084, 0x00000003},
63 {0x00000050, 0x00000000},
64 {0x00000040, 0xFFFFFFFF}
68 {0x00000000, 0x80000000},
69 {0x00000800, 0x80000001},
70 {0x00001000, 0x80000002},
[all …]
/openbmc/linux/include/linux/mfd/
H A Dezx-pcap.h40 #define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT 0x00000000
43 #define PCAP_REGISTER_VALUE_MASK 0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
47 #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
51 #define PCAP_REG_ISR 0x0 /* Interrupt Status */
52 #define PCAP_REG_MSR 0x1 /* Interrupt Mask */
53 #define PCAP_REG_PSTAT 0x2 /* Processor Status */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
[all …]
/openbmc/linux/Documentation/gpu/
H A Dkms-properties.csv7 ,,“left margin”,RANGE,"Min=0, Max=100",Connector,TBD
8 ,,“right margin”,RANGE,"Min=0, Max=100",Connector,TBD
9 ,,“top margin”,RANGE,"Min=0, Max=100",Connector,TBD
10 ,,“bottom margin”,RANGE,"Min=0, Max=100",Connector,TBD
11 ,,“brightness”,RANGE,"Min=0, Max=100",Connector,TBD
12 ,,“contrast”,RANGE,"Min=0, Max=100",Connector,TBD
13 ,,“flicker reduction”,RANGE,"Min=0, Max=100",Connector,TBD
14 ,,“overscan”,RANGE,"Min=0, Max=100",Connector,TBD
15 ,,“saturation”,RANGE,"Min=0, Max=100",Connector,TBD
16 ,,“hue”,RANGE,"Min=0, Max=100",Connector,TBD
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-spear/
H A Dspr_syscntl.h26 #define MODE_SHIFT 0x00000003
28 #define NORMAL 0x00000004
29 #define SLOW 0x00000002
30 #define DOZE 0x00000001
31 #define SLEEP 0x00000000
33 #define PLL_TIM 0x01FFFFFF
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/openbmc/linux/drivers/scsi/
H A Dgvp11.c33 #define TO_DMA_MASK(m) (~((unsigned long long)m & 0xffffffff))
51 static int gvp11_xfer_mask = 0;
64 static int scsi_alloc_out_of_range = 0; in dma_setup()
83 wh->dma_bounce_len = (scsi_pointer->this_residual + 511) & ~0x1ff; in dma_setup()
98 wh->dma_bounce_len = 0; in dma_setup()
144 wh->dma_bounce_len = 0; in dma_setup()
175 bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; in dma_setup()
183 return 0; in dma_setup()
216 wh->dma_bounce_len = 0; in dma_stop()
262 if (q & 0x08) /* bit 3 should always be clear */ in check_wd33c93()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/openbmc/linux/arch/mips/alchemy/common/
H A Dvss.c14 #define VSS_GATE 0x00 /* gate wait timers */
15 #define VSS_CLKRST 0x04 /* clock/block control */
16 #define VSS_FTR 0x08 /* footers */
18 #define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
[all …]
/openbmc/linux/arch/mips/cobalt/
H A Dsetup.c51 .start = 0x00,
52 .end = 0x1f,
57 .start = 0x60,
58 .end = 0x6f,
63 .start = 0x80,
64 .end = 0x8f,
69 .start = 0xc0,
70 .end = 0xdf,
87 ioport_resource.end = 0x01ffffff; in plat_mem_setup()
90 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) in plat_mem_setup()
[all …]
/openbmc/linux/arch/sh/boards/mach-se/7343/
H A Dsetup.c32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
/openbmc/linux/drivers/media/platform/ti/vpe/
H A Dsc.h13 #define CFG_SC0 0x0
14 #define CFG_INTERLACE_O (1 << 0)
30 #define CFG_SC1 0x4
31 #define CFG_ROW_ACC_INC_MASK 0x07ffffff
32 #define CFG_ROW_ACC_INC_SHIFT 0
34 #define CFG_SC2 0x08
35 #define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff
36 #define CFG_ROW_ACC_OFFSET_SHIFT 0
38 #define CFG_SC3 0x0c
39 #define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff
[all …]
/openbmc/linux/drivers/scsi/arm/
H A Doak.c51 while (((status = readw(base + STAT)) & 0x100)==0); in oakscsi_pwrite()
53 return 0; in oakscsi_pwrite()
62 while(len > 0) in oakscsi_pread()
67 timeout = 0x01FFFFFF; in oakscsi_pread()
69 while (((status = readw(base + STAT)) & 0x100)==0) in oakscsi_pread()
72 if(status & 0x200 || !timeout) in oakscsi_pread()
95 return 0; in oakscsi_pread()
185 { 0xffff, 0xffff }
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dnislands_smc.h125 #define NISLANDS_SMC_STROBE_RATIO 0x0F
126 #define NISLANDS_SMC_STROBE_ENABLE 0x10
128 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
129 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
130 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04
131 #define NISLANDS_SMC_MC_STUTTER_EN 0x08
154 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
188 #define NI_SMC_SOFT_REGISTERS_START 0x108
190 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
191 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC
[all …]
H A Dsislands_smc.h167 #define SISLANDS_SMC_STROBE_RATIO 0x0F
168 #define SISLANDS_SMC_STROBE_ENABLE 0x10
170 #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01
171 #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02
172 #define SISLANDS_SMC_MC_RTT_ENABLE 0x04
173 #define SISLANDS_SMC_MC_STUTTER_EN 0x08
174 #define SISLANDS_SMC_MC_PG_EN 0x10
196 #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
228 #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
229 #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC
[all …]
/openbmc/u-boot/include/configs/
H A Dedb93xx.h38 #define CONFIG_ENV_SECT_SIZE 0x00020000
42 #define CONFIG_ENV_SECT_SIZE 0x00020000
46 #define CONFIG_ENV_SECT_SIZE 0x00020000
50 #define CONFIG_ENV_SECT_SIZE 0x00040000
54 #define CONFIG_ENV_SECT_SIZE 0x00020000
58 #define CONFIG_ENV_SECT_SIZE 0x00040000
62 #define CONFIG_ENV_SECT_SIZE 0x00040000
66 #define CONFIG_ENV_SECT_SIZE 0x00020000
83 #define CONFIG_SYS_SERIAL0 0x808C0000
84 #define CONFIG_SYS_SERIAL1 0x808D0000
[all …]
H A DBSC9131RDB.h18 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
29 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
30 #define CONFIG_SPL_RELOC_STACK 0x00100000
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
32 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
62 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
63 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Doverlay.c71 * Note that this only works for the range [0, 180].
103 if (src_x != 0 || src_y != 0) { in verify_scaling()
109 return 0; in verify_scaling()
130 unsigned shift = drm->client.device.info.chipset >= 0x30 ? 1 : 3; in nv10_update_plane()
131 unsigned format = 0; in nv10_update_plane()
140 ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); in nv10_update_plane()
144 nvbo = nouveau_gem_object(fb->obj[0]); in nv10_update_plane()
152 nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0); in nv10_update_plane()
154 nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0); in nv10_update_plane()
175 nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); in nv10_update_plane()
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dke_counter.c25 * PCI BAR 0 Register I/O map
27 #define KE_RESET_REG(x) (0x00 + ((x) * 0x20))
28 #define KE_LATCH_REG(x) (0x00 + ((x) * 0x20))
29 #define KE_LSB_REG(x) (0x04 + ((x) * 0x20))
30 #define KE_MID_REG(x) (0x08 + ((x) * 0x20))
31 #define KE_MSB_REG(x) (0x0c + ((x) * 0x20))
32 #define KE_SIGN_REG(x) (0x10 + ((x) * 0x20))
33 #define KE_OSC_SEL_REG 0xf8
34 #define KE_OSC_SEL_CLK(x) (((x) & 0x3) << 0)
38 #define KE_DO_REG 0xfc
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsislands_smc.h163 #define SISLANDS_SMC_STROBE_RATIO 0x0F
164 #define SISLANDS_SMC_STROBE_ENABLE 0x10
166 #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01
167 #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02
168 #define SISLANDS_SMC_MC_RTT_ENABLE 0x04
169 #define SISLANDS_SMC_MC_STUTTER_EN 0x08
170 #define SISLANDS_SMC_MC_PG_EN 0x10
192 #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0
224 #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
225 #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_eeprom.h22 #define AR9300_EEP_VER 0xD000
23 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
24 #define AR9300_EEP_MINOR_VER_1 0x1
41 #define AR9300_EEPMISC_WOW 0x02
48 #define AR9300_PAPRD_RATE_MASK 0x01ffffff
49 #define AR9300_PAPRD_SCALE_1 0x0e000000
51 #define AR9300_PAPRD_SCALE_2 0x70000000
54 #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9
63 #define AR9300_PWR_TABLE_OFFSET 0
78 #define AR9300_BASE_ADDR_4K 0xfff
[all …]
H A Dar9003_phy.h23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
/openbmc/u-boot/include/
H A Dfsl_qe.h20 #define QE_DATAONLY_BASE 0
37 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
38 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
39 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
40 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
50 #define QE_CR_FLG 0x00010000
51 #define QE_RESET 0x80000000
52 #define QE_INIT_TX_RX 0x00000000
53 #define QE_INIT_RX 0x00000001
54 #define QE_INIT_TX 0x00000002
[all …]

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