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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7921/
H A Dpci.c16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
20 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
63 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
64 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
65 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
66 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
67 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ in __mt7921_reg_addr()
[all …]
/openbmc/linux/drivers/mtd/chips/
H A Djedec_probe.c27 #define AM29DL800BB 0x22CB
28 #define AM29DL800BT 0x224A
30 #define AM29F800BB 0x2258
31 #define AM29F800BT 0x22D6
32 #define AM29LV400BB 0x22BA
33 #define AM29LV400BT 0x22B9
34 #define AM29LV800BB 0x225B
35 #define AM29LV800BT 0x22DA
36 #define AM29LV160DT 0x22C4
37 #define AM29LV160DB 0x2249
[all …]
/openbmc/linux/arch/parisc/include/uapi/asm/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/openbmc/linux/include/uapi/asm-generic/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/openbmc/u-boot/arch/arm/mach-orion5x/
H A Dlowlevel_init.S17 #define SDRAM_CONFIG 0x3148400
18 #define SDRAM_MODE 0x62
19 #define SDRAM_CONTROL 0x4041000
20 #define SDRAM_TIME_CTRL_LOW 0x11602220
21 #define SDRAM_TIME_CTRL_HI 0x40c
22 #define SDRAM_OPEN_PAGE_EN 0x0
24 #define SDRAM_BANK0_SIZE 0x3ff0001
25 #define SDRAM_ADDR_CTRL 0x10
27 #define SDRAM_OP_NOP 0x05
28 #define SDRAM_OP_SETMODE 0x03
[all …]
/openbmc/qemu/linux-user/alpha/
H A Dtarget_mman.h4 #define TARGET_MAP_ANONYMOUS 0x10
5 #define TARGET_MAP_FIXED 0x100
6 #define TARGET_MAP_GROWSDOWN 0x01000
7 #define TARGET_MAP_DENYWRITE 0x02000
8 #define TARGET_MAP_EXECUTABLE 0x04000
9 #define TARGET_MAP_LOCKED 0x08000
10 #define TARGET_MAP_NORESERVE 0x10000
11 #define TARGET_MAP_POPULATE 0x20000
12 #define TARGET_MAP_NONBLOCK 0x40000
13 #define TARGET_MAP_STACK 0x80000
[all …]
/openbmc/linux/tools/arch/alpha/include/uapi/asm/
H A Dmman.h13 #define MADV_NORMAL 0
19 #define MAP_ANONYMOUS 0x10
20 #define MAP_DENYWRITE 0x02000
21 #define MAP_EXECUTABLE 0x04000
22 #define MAP_FILE 0
23 #define MAP_FIXED 0x100
24 #define MAP_GROWSDOWN 0x01000
25 #define MAP_HUGETLB 0x100000
26 #define MAP_LOCKED 0x08000
27 #define MAP_NONBLOCK 0x40000
[all …]
/openbmc/linux/arch/x86/events/
H A Dperf_event_flags.h5 PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
6 PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
7 PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
8 PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
9 PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
10 PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
11 PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
12 /* 0x00080 */
13 PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
14 PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmfd.txt29 the child's base address to 0, the physical address within parent's address
42 reg = <0x01000 0x1000>;
46 offset = <0x08>;
47 mask = <0x01>;
/openbmc/u-boot/arch/x86/include/asm/
H A Dlapic.h11 #define LAPIC_DEFAULT_BASE 0xfee00000
13 #define LAPIC_ID 0x020
14 #define LAPIC_LVR 0x030
16 #define LAPIC_TASKPRI 0x080
17 #define LAPIC_TPRI_MASK 0xff
19 #define LAPIC_RRR 0x0c0
21 #define LAPIC_SPIV 0x0f0
22 #define LAPIC_SPIV_ENABLE 0x100
24 #define LAPIC_ICR 0x300
25 #define LAPIC_DEST_SELF 0x40000
[all …]
/openbmc/u-boot/include/
H A Dmpc86xx.h12 #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
19 #define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4)
20 #define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000)
21 #define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008)
28 #define L2CR_L2E 0x80000000 /* bit 0 - enable */
29 #define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
30 #define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
31 #define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
32 #define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
33 #define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
[all …]
H A Dtsec.h23 #define TSEC_SIZE 0x40000
24 #define TSEC_MDIO_OFFSET 0x40000
26 #define TSEC_SIZE 0x01000
27 #define TSEC_MDIO_OFFSET 0x01000
30 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
77 #define TBI_CR 0x00
78 #define TBI_SR 0x01
79 #define TBI_ANA 0x04
80 #define TBI_ANLPBPA 0x05
81 #define TBI_ANEX 0x06
[all …]
/openbmc/linux/drivers/media/rc/
H A Dir-rc5-decoder.c50 return 0; in ir_rc5_decode()
61 return 0; in ir_rc5_decode()
88 return 0; in ir_rc5_decode()
117 return 0; in ir_rc5_decode()
119 xdata = (data->bits & 0x0003F) >> 0; in ir_rc5_decode()
120 command = (data->bits & 0x00FC0) >> 6; in ir_rc5_decode()
121 system = (data->bits & 0x1F000) >> 12; in ir_rc5_decode()
122 toggle = (data->bits & 0x20000) ? 1 : 0; in ir_rc5_decode()
123 command += (data->bits & 0x40000) ? 0 : 0x40; in ir_rc5_decode()
132 return 0; in ir_rc5_decode()
[all …]
/openbmc/linux/tools/testing/selftests/kvm/include/x86_64/
H A Dapic.h15 #define APIC_DEFAULT_GPA 0xfee00000ULL
18 #define MSR_IA32_APICBASE 0x0000001b
22 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
25 #define APIC_BASE_MSR 0x800
27 #define APIC_ID 0x20
28 #define APIC_LVR 0x30
29 #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF)
30 #define APIC_TASKPRI 0x80
31 #define APIC_PROCPRI 0xA0
32 #define APIC_EOI 0xB0
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbevf/
H A Dregs.h7 #define IXGBE_VFCTRL 0x00000
8 #define IXGBE_VFSTATUS 0x00008
9 #define IXGBE_VFLINKS 0x00010
10 #define IXGBE_VFFRTIMER 0x00048
11 #define IXGBE_VFRXMEMWRAP 0x03190
12 #define IXGBE_VTEICR 0x00100
13 #define IXGBE_VTEICS 0x00104
14 #define IXGBE_VTEIMS 0x00108
15 #define IXGBE_VTEIMC 0x0010C
16 #define IXGBE_VTEIAC 0x00110
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddisplay2.h94 u8 res[0xc];
112 #define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
113 #define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
115 #define SUNXI_DE2_MUX_GLB_REGS 0x00000
116 #define SUNXI_DE2_MUX_BLD_REGS 0x01000
117 #define SUNXI_DE2_MUX_CHAN_REGS 0x02000
118 #define SUNXI_DE2_MUX_CHAN_SZ 0x1000
119 #define SUNXI_DE2_MUX_VSU_REGS 0x20000
120 #define SUNXI_DE2_MUX_GSU1_REGS 0x30000
121 #define SUNXI_DE2_MUX_GSU2_REGS 0x40000
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dmpic.h14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
/openbmc/linux/arch/alpha/include/uapi/asm/
H A Dmman.h5 #define PROT_READ 0x1 /* page can be read */
6 #define PROT_WRITE 0x2 /* page can be written */
7 #define PROT_EXEC 0x4 /* page can be executed */
8 #define PROT_SEM 0x8 /* page may be used for atomic ops */
9 #define PROT_NONE 0x0 /* page can not be accessed */
10 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
11 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
13 /* 0x01 - 0x03 are defined in linux/mman.h */
14 #define MAP_TYPE 0x0f /* Mask for type of mapping (OSF/1 is _wrong_) */
15 #define MAP_FIXED 0x100 /* Interpret addr exactly */
[all …]
/openbmc/u-boot/drivers/net/fm/
H A Dfm.h15 #define OH_PORT_ID_BASE 0x01
17 #define RX_PORT_1G_BASE 0x08
19 #define RX_PORT_10G_BASE 0x10
20 #define RX_PORT_10G_BASE2 0x08
21 #define TX_PORT_1G_BASE 0x28
23 #define TX_PORT_10G_BASE 0x30
24 #define TX_PORT_10G_BASE2 0x28
25 #define MIIM_TIMEOUT 0xFFFF
33 #define FM_MURAM_RES_SIZE 0x01000
46 #define BD_LAST 0x0800
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dheart.h24 #define HEART_XKPHYS_BASE ((void *)(IO_BASE | 0x000000000ff00000ULL))
47 * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
49 * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
56 * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
58 * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
60 * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
62 * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
64 * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
79 struct ip30_heart_regs { /* 0x0ff00000 */
80 u64 mode; /* + 0x00000 */
[all …]
/openbmc/u-boot/drivers/mtd/
H A Djedec_flash.c23 #define AM29DL800BB 0x22CB
24 #define AM29DL800BT 0x224A
26 #define AM29F400BB 0x22AB
27 #define AM29F800BB 0x2258
28 #define AM29F800BT 0x22D6
29 #define AM29LV400BB 0x22BA
30 #define AM29LV400BT 0x22B9
31 #define AM29LV800BB 0x225B
32 #define AM29LV800BT 0x22DA
33 #define AM29LV160DT 0x22C4
[all …]
/openbmc/linux/arch/powerpc/include/uapi/asm/
H A Dtermbits.h48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]

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