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/openbmc/linux/sound/soc/codecs/
H A Drt1019.h11 #define RT1019_DEVICE_ID_VAL 0x1019
12 #define RT1019_DEVICE_ID_VAL2 0x6731
14 #define RT1019_RESET 0x0000
15 #define RT1019_IDS_CTRL 0x0011
16 #define RT1019_ASEL_CTRL 0x0013
17 #define RT1019_PWR_STRP_2 0x0019
18 #define RT1019_BEEP_TONE 0x001b
19 #define RT1019_VER_ID 0x005c
20 #define RT1019_VEND_ID_1 0x005e
21 #define RT1019_VEND_ID_2 0x005f
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmaxim,max98504.yaml34 default: 0
42 default: 0
45 and "timed hold" phase, the value must be from 0...6 (dB) range.
49 default: 0
51 Brownout attack hold phase time in ms, VBATBROWN_ATTK_HOLD, register 0x0018.
55 default: 0
57 Brownout timed hold phase time in ms, VBATBROWN_TIME_HOLD, register 0x0019.
61 default: 0
63 Brownout release phase step time in ms, VBATBROWN_RELEASE, register 0x001A.
77 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/media/platform/ti/vpe/
H A Dsc_coeff.h17 HS_UP_SCALE = 0,
31 0x001F, 0x1F90, 0x00D2, 0x06FE, 0x00D2, 0x1F90, 0x001F,
32 0x001C, 0x1F9E, 0x009F, 0x06FB, 0x0108, 0x1F82, 0x0022,
33 0x0019, 0x1FAC, 0x006F, 0x06F3, 0x0140, 0x1F74, 0x0025,
34 0x0016, 0x1FB9, 0x0041, 0x06E7, 0x017B, 0x1F66, 0x0028,
35 0x0013, 0x1FC6, 0x0017, 0x06D6, 0x01B7, 0x1F58, 0x002B,
36 0x0010, 0x1FD3, 0x1FEF, 0x06C0, 0x01F6, 0x1F4B, 0x002D,
37 0x000E, 0x1FDF, 0x1FCB, 0x06A5, 0x0235, 0x1F3F, 0x002F,
38 0x000B, 0x1FEA, 0x1FAA, 0x0686, 0x0277, 0x1F33, 0x0031,
39 0x0009, 0x1FF5, 0x1F8C, 0x0663, 0x02B8, 0x1F28, 0x0033,
[all …]
/openbmc/linux/net/bluetooth/
H A Dmgmt_config.c82 TLV_SET_U16(0x0000, def_page_scan_type), in read_def_system_config()
83 TLV_SET_U16(0x0001, def_page_scan_int), in read_def_system_config()
84 TLV_SET_U16(0x0002, def_page_scan_window), in read_def_system_config()
85 TLV_SET_U16(0x0003, def_inq_scan_type), in read_def_system_config()
86 TLV_SET_U16(0x0004, def_inq_scan_int), in read_def_system_config()
87 TLV_SET_U16(0x0005, def_inq_scan_window), in read_def_system_config()
88 TLV_SET_U16(0x0006, def_br_lsto), in read_def_system_config()
89 TLV_SET_U16(0x0007, def_page_timeout), in read_def_system_config()
90 TLV_SET_U16(0x0008, sniff_min_interval), in read_def_system_config()
91 TLV_SET_U16(0x0009, sniff_max_interval), in read_def_system_config()
[all …]
/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-digittrade.c17 { 0x0000, KEY_NUMERIC_9 },
18 { 0x0001, KEY_EPG }, /* EPG */
19 { 0x0002, KEY_VOLUMEDOWN }, /* Vol Dn */
20 { 0x0003, KEY_TEXT }, /* TELETEXT */
21 { 0x0004, KEY_NUMERIC_8 },
22 { 0x0005, KEY_MUTE }, /* MUTE */
23 { 0x0006, KEY_POWER2 }, /* POWER */
24 { 0x0009, KEY_ZOOM }, /* FULLSCREEN */
25 { 0x000a, KEY_RECORD }, /* RECORD */
26 { 0x000d, KEY_SUBTITLE }, /* SUBTITLE */
[all …]
H A Drc-nebula.c12 { 0x0000, KEY_NUMERIC_0 },
13 { 0x0001, KEY_NUMERIC_1 },
14 { 0x0002, KEY_NUMERIC_2 },
15 { 0x0003, KEY_NUMERIC_3 },
16 { 0x0004, KEY_NUMERIC_4 },
17 { 0x0005, KEY_NUMERIC_5 },
18 { 0x0006, KEY_NUMERIC_6 },
19 { 0x0007, KEY_NUMERIC_7 },
20 { 0x0008, KEY_NUMERIC_8 },
21 { 0x0009, KEY_NUMERIC_9 },
[all …]
H A Drc-azurewave-ad-tu700.c12 { 0x0000, KEY_TAB }, /* Tab */
13 { 0x0001, KEY_NUMERIC_2 },
14 { 0x0002, KEY_CHANNELDOWN },
15 { 0x0003, KEY_NUMERIC_1 },
16 { 0x0004, KEY_MENU }, /* Record List */
17 { 0x0005, KEY_CHANNELUP },
18 { 0x0006, KEY_NUMERIC_3 },
19 { 0x0007, KEY_SLEEP }, /* Hibernate */
20 { 0x0008, KEY_VIDEO }, /* A/V */
21 { 0x0009, KEY_NUMERIC_4 },
[all …]
H A Drc-digitalnow-tinytwin.c12 { 0x0000, KEY_MUTE }, /* [symbol speaker] */
13 { 0x0001, KEY_VOLUMEUP },
14 { 0x0002, KEY_POWER2 }, /* TV [power button] */
15 { 0x0003, KEY_NUMERIC_2 },
16 { 0x0004, KEY_NUMERIC_3 },
17 { 0x0005, KEY_NUMERIC_4 },
18 { 0x0006, KEY_NUMERIC_6 },
19 { 0x0007, KEY_NUMERIC_7 },
20 { 0x0008, KEY_NUMERIC_8 },
21 { 0x0009, KEY_NUMERIC_STAR }, /* [*] */
[all …]
/openbmc/linux/sound/pci/hda/
H A Dideapad_s740_helper.c5 { 0x20, AC_VERB_SET_COEF_INDEX, 0x10 },
6 { 0x20, AC_VERB_SET_PROC_COEF, 0x0320 },
7 { 0x20, AC_VERB_SET_COEF_INDEX, 0x24 },
8 { 0x20, AC_VERB_SET_PROC_COEF, 0x0041 },
9 { 0x20, AC_VERB_SET_COEF_INDEX, 0x24 },
10 { 0x20, AC_VERB_SET_PROC_COEF, 0x0041 },
11 { 0x20, AC_VERB_SET_COEF_INDEX, 0x29 },
12 { 0x20, AC_VERB_SET_COEF_INDEX, 0x29 },
13 { 0x20, AC_VERB_SET_COEF_INDEX, 0x26 },
14 { 0x20, AC_VERB_SET_PROC_COEF, 0x0000 },
[all …]
/openbmc/linux/drivers/net/phy/
H A Dmicrochip_t1s.c14 #define PHY_ID_LAN867X_REVB1 0x0007C162
15 #define PHY_ID_LAN865X_REVB0 0x0007C1B3
17 #define LAN867X_REG_STS2 0x0019
21 #define LAN865X_REG_CFGPARAM_ADDR 0x00D8
22 #define LAN865X_REG_CFGPARAM_DATA 0x00D9
23 #define LAN865X_REG_CFGPARAM_CTRL 0x00DA
24 #define LAN865X_REG_STS2 0x0019
30 * RMW 0x1F 0x00D0 0x0002 0x0E03
31 * RMW 0x1F 0x00D1 0x0000 0x0300
32 * RMW 0x1F 0x0084 0x3380 0xFFC0
[all …]
H A Ddp83640_reg.h8 /* #define PAGE0 0x0000 */
9 #define PHYCR2 0x001c /* PHY Control Register 2 */
11 #define PAGE4 0x0004
12 #define PTP_CTL 0x0014 /* PTP Control Register */
13 #define PTP_TDR 0x0015 /* PTP Time Data Register */
14 #define PTP_STS 0x0016 /* PTP Status Register */
15 #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
16 #define PTP_RATEL 0x0018 /* PTP Rate Low Register */
17 #define PTP_RATEH 0x0019 /* PTP Rate High Register */
18 #define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dhead_64.h9 .word 0xa1902000 | val
13 .word 0x81540000 | (N << 25)
15 #define KERNBASE 0x400000
23 #define __CHEETAH_ID 0x003e0014
24 #define __JALAPENO_ID 0x003e0016
25 #define __SERRANO_ID 0x003e0022
27 #define CHEETAH_MANUF 0x003e
28 #define CHEETAH_IMPL 0x0014 /* Ultra-III */
29 #define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
30 #define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dcxd2820r_c.c14 struct i2c_client *client = priv->client[0]; in cxd2820r_set_frontend_c()
21 { 0x00080, 0x01, 0xff }, in cxd2820r_set_frontend_c()
22 { 0x00081, 0x05, 0xff }, in cxd2820r_set_frontend_c()
23 { 0x00085, 0x07, 0xff }, in cxd2820r_set_frontend_c()
24 { 0x00088, 0x01, 0xff }, in cxd2820r_set_frontend_c()
26 { 0x00082, 0x20, 0x60 }, in cxd2820r_set_frontend_c()
27 { 0x1016a, 0x48, 0xff }, in cxd2820r_set_frontend_c()
28 { 0x100a5, 0x00, 0x01 }, in cxd2820r_set_frontend_c()
29 { 0x10020, 0x06, 0x07 }, in cxd2820r_set_frontend_c()
30 { 0x10059, 0x50, 0xff }, in cxd2820r_set_frontend_c()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv15.c33 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
34 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
35 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
36 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
37 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
38 { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
39 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
40 { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
41 { -1, -1, 0x005f, &nv04_gr_object }, /* blit */
42 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
[all …]
H A Dnv17.c33 { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
34 { -1, -1, 0x0019, &nv04_gr_object }, /* clip */
35 { -1, -1, 0x0030, &nv04_gr_object }, /* null */
36 { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
37 { -1, -1, 0x0043, &nv04_gr_object }, /* rop */
38 { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */
39 { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
40 { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */
41 { -1, -1, 0x005f, &nv04_gr_object }, /* blit */
42 { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
[all …]
H A Dnv44.c42 case 0x44: in nv44_gr_tile()
43 case 0x4a: in nv44_gr_tile()
48 case 0x46: in nv44_gr_tile()
49 case 0x4c: in nv44_gr_tile()
50 case 0x63: in nv44_gr_tile()
51 case 0x67: in nv44_gr_tile()
52 case 0x68: in nv44_gr_tile()
60 case 0x4e: in nv44_gr_tile()
84 { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */
85 { -1, -1, 0x0019, &nv40_gr_object }, /* clip */
[all …]
/openbmc/linux/include/linux/mfd/
H A Dlochnagar1_regs.h15 #define LOCHNAGAR1_CDC_AIF1_SEL 0x0008
16 #define LOCHNAGAR1_CDC_AIF2_SEL 0x0009
17 #define LOCHNAGAR1_CDC_AIF3_SEL 0x000A
18 #define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B
19 #define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C
20 #define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D
21 #define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E
22 #define LOCHNAGAR1_EXT_AIF_CTRL 0x000F
23 #define LOCHNAGAR1_DSP_AIF1_SEL 0x0010
24 #define LOCHNAGAR1_DSP_AIF2_SEL 0x0011
[all …]
/openbmc/linux/include/rdma/
H A Dib_smi.h39 #define IB_SMP_DIRECTION cpu_to_be16(0x8000)
42 #define IB_SMP_ATTR_NOTICE cpu_to_be16(0x0002)
43 #define IB_SMP_ATTR_NODE_DESC cpu_to_be16(0x0010)
44 #define IB_SMP_ATTR_NODE_INFO cpu_to_be16(0x0011)
45 #define IB_SMP_ATTR_SWITCH_INFO cpu_to_be16(0x0012)
46 #define IB_SMP_ATTR_GUID_INFO cpu_to_be16(0x0014)
47 #define IB_SMP_ATTR_PORT_INFO cpu_to_be16(0x0015)
48 #define IB_SMP_ATTR_PKEY_TABLE cpu_to_be16(0x0016)
49 #define IB_SMP_ATTR_SL_TO_VL_TABLE cpu_to_be16(0x0017)
50 #define IB_SMP_ATTR_VL_ARB_TABLE cpu_to_be16(0x0018)
[all …]
/openbmc/linux/include/acpi/
H A Dacexcep.h18 #define AE_CODE_ENVIRONMENTAL 0x0000 /* General ACPICA environment */
19 #define AE_CODE_PROGRAMMER 0x1000 /* External ACPICA interface caller */
20 #define AE_CODE_ACPI_TABLES 0x2000 /* ACPI tables */
21 #define AE_CODE_AML 0x3000 /* From executing AML code */
22 #define AE_CODE_CONTROL 0x4000 /* Internal control codes */
24 #define AE_CODE_MAX 0x4000
25 #define AE_CODE_MASK 0xF000
60 #define AE_OK (acpi_status) 0x0000
71 #define AE_ERROR EXCEP_ENV (0x0001)
72 #define AE_NO_ACPI_TABLES EXCEP_ENV (0x0002)
[all …]
/openbmc/linux/include/linux/sunrpc/
H A Dgss_krb5.h60 #define KG_TOK_MIC_MSG 0x0101
61 #define KG_TOK_WRAP_MSG 0x0201
63 #define KG2_TOK_INITIAL 0x0101
64 #define KG2_TOK_RESPONSE 0x0202
65 #define KG2_TOK_MIC 0x0404
66 #define KG2_TOK_WRAP 0x0504
68 #define KG2_TOKEN_FLAG_SENTBYACCEPTOR 0x01
69 #define KG2_TOKEN_FLAG_SEALED 0x02
70 #define KG2_TOKEN_FLAG_ACCEPTORSUBKEY 0x04
72 #define KG2_RESP_FLAG_ERROR 0x0001
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Dsdio.h10 #define SDIO_LOCAL_OFFSET 0x10250000
11 #define WLAN_IOREG_OFFSET 0x10260000
12 #define FIRMWARE_FIFO_OFFSET 0x10270000
13 #define TX_HIQ_OFFSET 0x10310000
14 #define TX_MIQ_OFFSET 0x10320000
15 #define TX_LOQ_OFFSET 0x10330000
16 #define TX_EPQ_OFFSET 0x10350000
17 #define RX_RX0FF_OFFSET 0x10340000
19 #define RTW_SDIO_BUS_MSK 0xffff0000
20 #define SDIO_LOCAL_REG_MSK 0x00000fff
[all …]
/openbmc/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c36 #define DP_PLL0 BIT(0)
39 #define TORRENT_COMMON_CDB_OFFSET 0x0
42 ((0x4000 << (block_offset)) + \
46 ((0x8000 << (block_offset)) + \
50 (0xC000 << (block_offset))
53 ((0xD000 << (block_offset)) + \
57 (0xE000 << (block_offset))
59 #define TORRENT_DPTX_PHY_OFFSET 0x0
63 * register base + 0x30a00)
65 #define PHY_AUX_CTRL 0x04
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Dosssys_4_4_2_offset.h29 // base address: 0x4280
30 …IH_VMID_0_LUT 0x0000
31 …e regIH_VMID_0_LUT_BASE_IDX 0
32 …IH_VMID_1_LUT 0x0001
33 …e regIH_VMID_1_LUT_BASE_IDX 0
34 …IH_VMID_2_LUT 0x0002
35 …e regIH_VMID_2_LUT_BASE_IDX 0
36 …IH_VMID_3_LUT 0x0003
37 …e regIH_VMID_3_LUT_BASE_IDX 0
38 …IH_VMID_4_LUT 0x0004
[all …]
H A Dosssys_6_0_0_offset.h29 // base address: 0x4280
30 …IH_VMID_0_LUT 0x0000
31 …e regIH_VMID_0_LUT_BASE_IDX 0
32 …IH_VMID_1_LUT 0x0001
33 …e regIH_VMID_1_LUT_BASE_IDX 0
34 …IH_VMID_2_LUT 0x0002
35 …e regIH_VMID_2_LUT_BASE_IDX 0
36 …IH_VMID_3_LUT 0x0003
37 …e regIH_VMID_3_LUT_BASE_IDX 0
38 …IH_VMID_4_LUT 0x0004
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/thm/
H A Dthm_10_0_offset.h27 // base address: 0x59800
28 …THM_TCON_CUR_TMP 0x0000
29 …ne mmTHM_TCON_CUR_TMP_BASE_IDX 0
30 …THM_TCON_HTC 0x0001
31 …ne mmTHM_TCON_HTC_BASE_IDX 0
32 …THM_TCON_THERM_TRIP 0x0002
33 …ne mmTHM_TCON_THERM_TRIP_BASE_IDX 0
34 …THM_CTF_DELAY 0x0003
35 …ne mmTHM_CTF_DELAY_BASE_IDX 0
36 …THM_GPIO_PROCHOT_CTRL 0x0004
[all …]

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