Lines Matching +full:0 +full:x0019
8 /* #define PAGE0 0x0000 */
9 #define PHYCR2 0x001c /* PHY Control Register 2 */
11 #define PAGE4 0x0004
12 #define PTP_CTL 0x0014 /* PTP Control Register */
13 #define PTP_TDR 0x0015 /* PTP Time Data Register */
14 #define PTP_STS 0x0016 /* PTP Status Register */
15 #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
16 #define PTP_RATEL 0x0018 /* PTP Rate Low Register */
17 #define PTP_RATEH 0x0019 /* PTP Rate High Register */
18 #define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
19 #define PTP_WRCKSUM 0x001b /* PTP Write Checksum */
20 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
22 #define PTP_ESTS 0x001e /* PTP Event Status Register */
23 #define PTP_EDATA 0x001f /* PTP Event Data Register */
25 #define PAGE5 0x0005
26 #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
27 #define PTP_EVNT 0x0015 /* PTP Event Configuration Register */
28 #define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */
29 #define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */
30 #define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
31 #define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */
32 #define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */
33 #define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */
34 #define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */
35 #define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */
36 #define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
37 #define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
39 #define PAGE6 0x0006
40 #define PTP_COC 0x0014 /* PTP Clock Output Control Register */
41 #define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
42 #define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
43 #define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
44 #define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */
45 #define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */
46 #define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */
47 #define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
48 #define PTP_ETR 0x001c /* PTP Ethernet Type Register */
49 #define PTP_OFF 0x001d /* PTP Offset Register */
50 #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */
51 #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */
58 #define TRIG_SEL_MASK (0x7)
68 #define PTP_RESET (1<<0) /* Reset PTP Clock */
78 #define EVENT_IE (1<<0) /* Event Interrupt Enable */
95 #define TRIG0_ERROR (1<<1) /* Trigger 0 Error */
96 #define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
101 #define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
102 #define PTP_RATE_HI_MASK (0x3ff)
106 #define EVNTS_MISSED_MASK (0x7)
108 #define EVNT_TS_LEN_MASK (0x3)
111 #define EVNT_NUM_MASK (0x7)
113 #define EVENT_DET (1<<0) /* PTP Event Detected */
130 #define E0_RISE (1<<1) /* Indicates direction of Event 0 */
131 #define E0_DET (1<<0) /* Indicates Event 0 detected */
139 #define TRIG_GPIO_MASK (0xf)
142 #define TRIG_CSEL_MASK (0x7)
143 #define TRIG_WR (1<<0) /* Trigger Configuration Write */
150 #define EVNT_GPIO_MASK (0xf)
152 #define EVNT_SEL_MASK (0x7)
153 #define EVNT_WR (1<<0) /* Event Configuration Write */
167 #define TX_PTP_VER_MASK (0xf)
168 #define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
172 #define BYTE0_MASK_MASK (0xff)
173 #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message …
174 #define BYTE0_DATA_MASK (0xff)
178 #define MAC_SRC_ADD_MASK (0x3)
180 #define MIN_PRE_MASK (0x7)
188 #define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
197 #define IP1588_EN_MASK (0xf)
202 #define RX_PTP_VER_MASK (0xf)
203 #define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
207 #define BYTE0_MASK_MASK (0xff)
208 #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message …
209 #define BYTE0_DATA_MASK (0xff)
213 #define TS_MIN_IFG_MASK (0xf)
218 #define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */
219 #define PTP_DOMAIN_MASK (0xff)
225 #define TS_SEC_LEN_MASK (0x3)
227 #define RXTS_NS_OFF_MASK (0x3f)
228 #define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */
229 #define RXTS_SEC_OFF_MASK (0x3f)
235 #define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
236 #define PTP_CLKDIV_MASK (0xff)
240 #define PTPRESERVED_MASK (0xf)
242 #define VERSIONPTP_MASK (0xf)
244 #define TRANSPORT_SPECIFIC_MASK (0xf)
245 #define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */
246 #define MESSAGETYPE_MASK (0xf)
250 #define TX_SFD_GPIO_MASK (0xf)
251 #define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */
252 #define RX_SFD_GPIO_MASK (0xf)
255 #define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */
256 #define PTP_INT_GPIO_MASK (0xf)
260 #define CLK_SRC_MASK (0x3)
261 #define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
262 #define CLK_SRC_PER_MASK (0x7f)
265 #define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */
266 #define PTP_OFFSET_MASK (0xff)