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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml175 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
202 - description: host1x syncpoint interrupt 0
226 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
240 reg = <0x50000000 0x00024000>;
241 interrupts = <0 65 0x04>, /* mpcore syncpt */
242 <0 67 0x04>; /* mpcore general */
252 ranges = <0x54000000 0x54000000 0x04000000>;
256 reg = <0x54040000 0x00040000>;
257 interrupts = <0 68 0x04>;
265 reg = <0x54080000 0x00040000>;
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt244 reg = <0x50000000 0x00024000>;
245 interrupts = <0 65 0x04 /* mpcore syncpt */
246 0 67 0x04>; /* mpcore general */
254 ranges = <0x54000000 0x54000000 0x04000000>;
258 reg = <0x54040000 0x00040000>;
259 interrupts = <0 68 0x04>;
267 reg = <0x54080000 0x00040000>;
268 interrupts = <0 69 0x04>;
276 reg = <0x540c0000 0x00040000>;
277 interrupts = <0 70 0x04>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
H A Dmpc8572ds.dts19 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
22 0x1 0x0 0x0 0xe0000000 0x08000000
23 0x2 0x0 0x0 0xffa00000 0x00040000
24 0x3 0x0 0x0 0xffdf0000 0x00008000
25 0x4 0x0 0x0 0xffa40000 0x00040000
26 0x5 0x0 0x0 0xffa80000 0x00040000
27 0x6 0x0 0x0 0xffac0000 0x00040000>;
31 ranges = <0x0 0 0xffe00000 0x100000>;
35 reg = <0 0xffe08000 0 0x1000>;
[all …]
H A Dmpc8572ds_36b.dts19 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
35 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
/openbmc/linux/sound/pci/
H A Dsis7019.h17 #define SIS_GCR 0x00
18 #define SIS_GCR_MACRO_POWER_DOWN 0x80000000
19 #define SIS_GCR_MODEM_ENABLE 0x00010000
20 #define SIS_GCR_SOFTWARE_RESET 0x00000001
23 #define SIS_GIER 0x04
24 #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000
25 #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000
26 #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000
27 #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000
28 #define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra210.dtsi17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29 bus-range = <0x00 0xff>;
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
[all …]
H A Dtegra20.dtsi14 reg = <0x50000000 0x00024000>;
24 ranges = <0x54000000 0x54000000 0x04000000>;
28 reg = <0x54040000 0x00040000>;
37 reg = <0x54080000 0x00040000>;
46 reg = <0x540c0000 0x00040000>;
55 reg = <0x54100000 0x00040000>;
64 reg = <0x54140000 0x00040000>;
73 reg = <0x54180000 0x00040000>;
81 reg = <0x54200000 0x00040000>;
89 nvidia,head = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d27_som1.dtsi39 pinctrl-0 = <&pinctrl_qspi1_default>;
41 flash@0 {
45 reg = <0>;
52 at91bootstrap@0 {
54 reg = <0x00000000 0x00040000>;
59 reg = <0x00040000 0x000c0000>;
64 reg = <0x00100000 0x00040000>;
69 reg = <0x00140000 0x00040000>;
74 reg = <0x00180000 0x00080000>;
79 reg = <0x00200000 0x00600000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
/openbmc/u-boot/board/sr1500/qts/
H A Diocsr_config.h15 0x00100000,
16 0x40000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x000E0180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
/openbmc/u-boot/board/freescale/mx7ulp_evk/
H A Dimximage.cfg27 PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
44 DATA 4 0x403f00dc 0x00000000
45 DATA 4 0x403e0040 0x01000020
46 DATA 4 0x403e0500 0x01000000
47 DATA 4 0x403e050c 0x80808080
48 DATA 4 0x403e0508 0x00140000
49 DATA 4 0x403E0510 0x00000004
50 DATA 4 0x403E0514 0x00000002
51 DATA 4 0x403e0500 0x00000001
52 CHECK_BITS_SET 4 0x403e0500 0x01000000
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h16 #define FSL_DMA_MR_CS 0x00000001 /* Channel start */
17 #define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
18 #define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
19 #define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
20 #define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
21 #define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
22 #define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
23 #define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
24 #define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
25 #define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dprocessor-flags.h8 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
9 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
10 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
11 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
12 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
13 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
14 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
15 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
16 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
17 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
[all …]
/openbmc/u-boot/board/work-microwave/work_92105/
H A DREADME24 1. spl/u-boot-spl.bin SPL, intended to run from SRAM at address 0.
38 at offset 0x00040000 in NAND.
52 in NAND at addresses 0x00000000 and 0x00020000
55 5. lpc32xx-boot-0.bin lpc32xx-spl.img, padded with 0xFF bytes to a
56 size of 0x20000 bytes. This file covers exactly
60 6. lpc32xx-boot-1.bin Same as lpc32xx-boot-0.bin. This is intended to
63 7. lpc32xx-full.bin lpc32xx-boot-0.bin, lpc32xx-boot-1.bin and
76 nand erase 0x00000000 0x80000
78 nand write $loadaddr 0x00000000 $filesize
82 nand erase 0x00000000 0x40000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dti,gpmc-nand.yaml65 "@[0-9a-f]+$":
85 dmas = <&edma 52 0>;
89 reg = <0x50000000 0x2000>;
100 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
101 nand@0,0 {
103 reg = <0 0 4>; /* device IO registers */
105 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
115 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
120 partition@0 {
122 reg = <0x00000000 0x00040000>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_0_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_default.h26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata_priv.h22 #define SATA_HOST_CAP_S64A 0x80000000
23 #define SATA_HOST_CAP_SNCQ 0x40000000
24 #define SATA_HOST_CAP_SSNTF 0x20000000
25 #define SATA_HOST_CAP_SMPS 0x10000000
26 #define SATA_HOST_CAP_SSS 0x08000000
27 #define SATA_HOST_CAP_SALP 0x04000000
28 #define SATA_HOST_CAP_SAL 0x02000000
29 #define SATA_HOST_CAP_SCLO 0x01000000
30 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
32 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
/openbmc/linux/arch/powerpc/platforms/8xx/
H A Dmpc885ads.h22 #define BCSR1_ETHEN ((uint)0x20000000)
23 #define BCSR1_IRDAEN ((uint)0x10000000)
24 #define BCSR1_RS232EN_1 ((uint)0x01000000)
25 #define BCSR1_PCCEN ((uint)0x00800000)
26 #define BCSR1_PCCVCC0 ((uint)0x00400000)
27 #define BCSR1_PCCVPP0 ((uint)0x00200000)
28 #define BCSR1_PCCVPP1 ((uint)0x00100000)
30 #define BCSR1_RS232EN_2 ((uint)0x00040000)
31 #define BCSR1_PCCVCC1 ((uint)0x00010000)
34 #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
[all …]
H A Dmpc86xads.h20 #define BCSR1_ETHEN ((uint)0x20000000)
21 #define BCSR1_IRDAEN ((uint)0x10000000)
22 #define BCSR1_RS232EN_1 ((uint)0x01000000)
23 #define BCSR1_PCCEN ((uint)0x00800000)
24 #define BCSR1_PCCVCC0 ((uint)0x00400000)
25 #define BCSR1_PCCVPP0 ((uint)0x00200000)
26 #define BCSR1_PCCVPP1 ((uint)0x00100000)
28 #define BCSR1_RS232EN_2 ((uint)0x00040000)
29 #define BCSR1_PCCVCC1 ((uint)0x00010000)
32 #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
[all …]

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