1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
4*724ba675SRob Herring *
5*724ba675SRob Herring *  Copyright (c) 2017, Microchip Technology Inc.
6*724ba675SRob Herring *                2017 Cristian Birsan <cristian.birsan@microchip.com>
7*724ba675SRob Herring *                2017 Claudiu Beznea <claudiu.beznea@microchip.com>
8*724ba675SRob Herring */
9*724ba675SRob Herring#include "sama5d2.dtsi"
10*724ba675SRob Herring#include "sama5d2-pinfunc.h"
11*724ba675SRob Herring#include <dt-bindings/gpio/gpio.h>
12*724ba675SRob Herring
13*724ba675SRob Herring/ {
14*724ba675SRob Herring	model = "Atmel SAMA5D27 SoM1";
15*724ba675SRob Herring	compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
16*724ba675SRob Herring
17*724ba675SRob Herring	aliases {
18*724ba675SRob Herring		i2c0 = &i2c0;
19*724ba675SRob Herring	};
20*724ba675SRob Herring
21*724ba675SRob Herring	clocks {
22*724ba675SRob Herring		slow_xtal {
23*724ba675SRob Herring			clock-frequency = <32768>;
24*724ba675SRob Herring		};
25*724ba675SRob Herring
26*724ba675SRob Herring		main_xtal {
27*724ba675SRob Herring			clock-frequency = <24000000>;
28*724ba675SRob Herring		};
29*724ba675SRob Herring	};
30*724ba675SRob Herring
31*724ba675SRob Herring	ahb {
32*724ba675SRob Herring		sdmmc0: sdio-host@a0000000 {
33*724ba675SRob Herring			microchip,sdcal-inverted;
34*724ba675SRob Herring		};
35*724ba675SRob Herring
36*724ba675SRob Herring		apb {
37*724ba675SRob Herring			qspi1: spi@f0024000 {
38*724ba675SRob Herring				pinctrl-names = "default";
39*724ba675SRob Herring				pinctrl-0 = <&pinctrl_qspi1_default>;
40*724ba675SRob Herring
41*724ba675SRob Herring				flash@0 {
42*724ba675SRob Herring					#address-cells = <1>;
43*724ba675SRob Herring					#size-cells = <1>;
44*724ba675SRob Herring					compatible = "jedec,spi-nor";
45*724ba675SRob Herring					reg = <0>;
46*724ba675SRob Herring					spi-max-frequency = <104000000>;
47*724ba675SRob Herring					spi-cs-setup-ns = <7>;
48*724ba675SRob Herring					spi-tx-bus-width = <4>;
49*724ba675SRob Herring					spi-rx-bus-width = <4>;
50*724ba675SRob Herring					m25p,fast-read;
51*724ba675SRob Herring
52*724ba675SRob Herring					at91bootstrap@0 {
53*724ba675SRob Herring						label = "at91bootstrap";
54*724ba675SRob Herring						reg = <0x00000000 0x00040000>;
55*724ba675SRob Herring					};
56*724ba675SRob Herring
57*724ba675SRob Herring					bootloader@40000 {
58*724ba675SRob Herring						label = "bootloader";
59*724ba675SRob Herring						reg = <0x00040000 0x000c0000>;
60*724ba675SRob Herring					};
61*724ba675SRob Herring
62*724ba675SRob Herring					bootloaderenvred@100000 {
63*724ba675SRob Herring						label = "bootloader env redundant";
64*724ba675SRob Herring						reg = <0x00100000 0x00040000>;
65*724ba675SRob Herring					};
66*724ba675SRob Herring
67*724ba675SRob Herring					bootloaderenv@140000 {
68*724ba675SRob Herring						label = "bootloader env";
69*724ba675SRob Herring						reg = <0x00140000 0x00040000>;
70*724ba675SRob Herring					};
71*724ba675SRob Herring
72*724ba675SRob Herring					dtb@180000 {
73*724ba675SRob Herring						label = "device tree";
74*724ba675SRob Herring						reg = <0x00180000 0x00080000>;
75*724ba675SRob Herring					};
76*724ba675SRob Herring
77*724ba675SRob Herring					kernel@200000 {
78*724ba675SRob Herring						label = "kernel";
79*724ba675SRob Herring						reg = <0x00200000 0x00600000>;
80*724ba675SRob Herring					};
81*724ba675SRob Herring				};
82*724ba675SRob Herring			};
83*724ba675SRob Herring
84*724ba675SRob Herring			macb0: ethernet@f8008000 {
85*724ba675SRob Herring				pinctrl-names = "default";
86*724ba675SRob Herring				pinctrl-0 = <&pinctrl_macb0_default>;
87*724ba675SRob Herring				#address-cells = <1>;
88*724ba675SRob Herring				#size-cells = <0>;
89*724ba675SRob Herring				phy-mode = "rmii";
90*724ba675SRob Herring
91*724ba675SRob Herring				ethernet-phy@7 {
92*724ba675SRob Herring					reg = <0x7>;
93*724ba675SRob Herring					interrupt-parent = <&pioA>;
94*724ba675SRob Herring					interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
95*724ba675SRob Herring					pinctrl-names = "default";
96*724ba675SRob Herring					pinctrl-0 = <&pinctrl_macb0_phy_irq>;
97*724ba675SRob Herring				};
98*724ba675SRob Herring			};
99*724ba675SRob Herring
100*724ba675SRob Herring			i2c0: i2c@f8028000 {
101*724ba675SRob Herring				dmas = <0>, <0>;
102*724ba675SRob Herring				pinctrl-names = "default", "gpio";
103*724ba675SRob Herring				pinctrl-0 = <&pinctrl_i2c0_default>;
104*724ba675SRob Herring				pinctrl-1 = <&pinctrl_i2c0_gpio>;
105*724ba675SRob Herring				sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
106*724ba675SRob Herring				scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
107*724ba675SRob Herring				status = "okay";
108*724ba675SRob Herring
109*724ba675SRob Herring				at24@50 {
110*724ba675SRob Herring					compatible = "atmel,24c02";
111*724ba675SRob Herring					reg = <0x50>;
112*724ba675SRob Herring					pagesize = <8>;
113*724ba675SRob Herring				};
114*724ba675SRob Herring			};
115*724ba675SRob Herring
116*724ba675SRob Herring			pinctrl@fc038000 {
117*724ba675SRob Herring				pinctrl_i2c0_default: i2c0_default {
118*724ba675SRob Herring					pinmux = <PIN_PD21__TWD0>,
119*724ba675SRob Herring						 <PIN_PD22__TWCK0>;
120*724ba675SRob Herring					bias-disable;
121*724ba675SRob Herring				};
122*724ba675SRob Herring
123*724ba675SRob Herring				pinctrl_i2c0_gpio: i2c0_gpio {
124*724ba675SRob Herring					pinmux = <PIN_PD21__GPIO>,
125*724ba675SRob Herring						 <PIN_PD22__GPIO>;
126*724ba675SRob Herring					bias-disable;
127*724ba675SRob Herring				};
128*724ba675SRob Herring
129*724ba675SRob Herring				pinctrl_qspi1_default: qspi1_default {
130*724ba675SRob Herring					sck_cs {
131*724ba675SRob Herring						pinmux = <PIN_PB5__QSPI1_SCK>,
132*724ba675SRob Herring							 <PIN_PB6__QSPI1_CS>;
133*724ba675SRob Herring						bias-disable;
134*724ba675SRob Herring					};
135*724ba675SRob Herring
136*724ba675SRob Herring					data {
137*724ba675SRob Herring						pinmux = <PIN_PB7__QSPI1_IO0>,
138*724ba675SRob Herring							 <PIN_PB8__QSPI1_IO1>,
139*724ba675SRob Herring							 <PIN_PB9__QSPI1_IO2>,
140*724ba675SRob Herring							 <PIN_PB10__QSPI1_IO3>;
141*724ba675SRob Herring						bias-pull-up;
142*724ba675SRob Herring					};
143*724ba675SRob Herring				};
144*724ba675SRob Herring
145*724ba675SRob Herring				pinctrl_macb0_default: macb0_default {
146*724ba675SRob Herring					pinmux = <PIN_PD9__GTXCK>,
147*724ba675SRob Herring						 <PIN_PD10__GTXEN>,
148*724ba675SRob Herring						 <PIN_PD11__GRXDV>,
149*724ba675SRob Herring						 <PIN_PD12__GRXER>,
150*724ba675SRob Herring						 <PIN_PD13__GRX0>,
151*724ba675SRob Herring						 <PIN_PD14__GRX1>,
152*724ba675SRob Herring						 <PIN_PD15__GTX0>,
153*724ba675SRob Herring						 <PIN_PD16__GTX1>,
154*724ba675SRob Herring						 <PIN_PD17__GMDC>,
155*724ba675SRob Herring						 <PIN_PD18__GMDIO>;
156*724ba675SRob Herring					bias-disable;
157*724ba675SRob Herring				};
158*724ba675SRob Herring
159*724ba675SRob Herring				pinctrl_macb0_phy_irq: macb0_phy_irq {
160*724ba675SRob Herring					pinmux = <PIN_PD31__GPIO>;
161*724ba675SRob Herring					bias-disable;
162*724ba675SRob Herring				};
163*724ba675SRob Herring			};
164*724ba675SRob Herring		};
165*724ba675SRob Herring	};
166*724ba675SRob Herring};
167