Home
last modified time | relevance | path

Searched +full:0 +full:x00020002 (Results 1 – 25 of 42) sorted by relevance

12

/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654-base-board-ddr4-1600MHz.dtsi13 #define DDRCTL_MSTR 0x41040010
14 #define DDRCTL_RFSHCTL0 0x00210070
15 #define DDRCTL_ECCCFG0 0x00000000
16 #define DDRCTL_RFSHTMG 0x0061008C
17 #define DDRCTL_CRCPARCTL0 0x00008000
18 #define DDRCTL_CRCPARCTL1 0x1A000000
19 #define DDRCTL_CRCPARCTL2 0x0048051E
20 #define DDRCTL_INIT0 0x400100C4
21 #define DDRCTL_INIT1 0x004F0000
22 #define DDRCTL_INIT3 0x02140501
[all …]
H A Dfsl-imx8mq.dtsi47 reg = <0x00000000 0x40000000 0 0xc0000000>;
52 reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
53 <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
82 reg = <0x0 0x30670000 0x0 0x10000>;
93 reg = <0x0 0x30200000 0x0 0x10000>;
104 reg = <0x0 0x30210000 0x0 0x10000>;
115 reg = <0x0 0x30220000 0x0 0x10000>;
126 reg = <0x0 0x30230000 0x0 0x10000>;
137 reg = <0x0 0x30240000 0x0 0x10000>;
148 reg = <0x0 0x30260000 0x0 0x10000>;
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-firmware.c17 #define CX18_PROC_SOFT_RESET 0xc70010
18 #define CX18_DDR_SOFT_RESET 0xc70014
19 #define CX18_CLOCK_SELECT1 0xc71000
20 #define CX18_CLOCK_SELECT2 0xc71004
21 #define CX18_HALF_CLOCK_SELECT1 0xc71008
22 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
23 #define CX18_CLOCK_POLARITY1 0xc71010
24 #define CX18_CLOCK_POLARITY2 0xc71014
25 #define CX18_ADD_DELAY_ENABLE1 0xc71018
26 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dtest_vavgw.S4 * 0x00030001 averaged with 0x00010003 results 0x00020002.
20 r1:0 = vavgw(r1:0, r3:2):crnd
/openbmc/linux/sound/pci/ice1712/
H A Dpontis.h15 #define VT1720_SUBDEVICE_PONTIS_MS300 0x00020002 /* a dummy id for MS300 */
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dtimer_defs.h36 #define DV_WDT_ENABLE_SYS_RESET 0x00020000
37 #define DV_WDT_TRIGGER_SYS_RESET 0x00020002
/openbmc/linux/drivers/gpu/drm/vmwgfx/device_include/
H A Dsvga_overlay.h44 #define VMWARE_FOURCC_YV12 0x32315659
45 #define VMWARE_FOURCC_YUY2 0x32595559
46 #define VMWARE_FOURCC_UYVY 0x59565955
49 SVGA_OVERLAY_FORMAT_INVALID = 0,
55 #define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
57 #define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
59 #define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
61 #define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/openbmc/qemu/include/hw/arm/
H A Draspberrypi-fw-defs.h15 RPI_FWREQ_PROPERTY_END = 0,
16 RPI_FWREQ_GET_FIRMWARE_REVISION = 0x00000001,
17 RPI_FWREQ_GET_FIRMWARE_VARIANT = 0x00000002,
18 RPI_FWREQ_GET_FIRMWARE_HASH = 0x00000003,
20 RPI_FWREQ_SET_CURSOR_INFO = 0x00008010,
21 RPI_FWREQ_SET_CURSOR_STATE = 0x00008011,
23 RPI_FWREQ_GET_BOARD_MODEL = 0x00010001,
24 RPI_FWREQ_GET_BOARD_REVISION = 0x00010002,
25 RPI_FWREQ_GET_BOARD_MAC_ADDRESS = 0x00010003,
26 RPI_FWREQ_GET_BOARD_SERIAL = 0x00010004,
[all …]
/openbmc/linux/include/soc/bcm2835/
H A Draspberrypi-firmware.h15 RPI_FIRMWARE_STATUS_REQUEST = 0,
16 RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000,
17 RPI_FIRMWARE_STATUS_ERROR = 0x80000001,
37 RPI_FIRMWARE_PROPERTY_END = 0,
38 RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001,
40 RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010,
41 RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011,
43 RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001,
44 RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002,
45 RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_2_0_0_default.h26 #define mmATC_ATS_CNTL_DEFAULT 0x009a0c00
27 #define mmATC_ATS_STATUS_DEFAULT 0x00000000
28 #define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff
29 #define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000
30 #define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000
31 #define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000
32 #define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff
33 #define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000
34 #define mmATHUB_MISC_CNTL_DEFAULT 0x001c0200
35 #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000
[all …]
/openbmc/u-boot/board/renesas/blanche/
H A Dblanche.c32 #define CPG_PLL1CR 0xE6150028
33 #define CPG_PLL3CR 0xE61500DC
50 if (cpu_type == 0x4A) { in blanche_init_sys()
51 writel(0x4D000000, CPG_PLL1CR); in blanche_init_sys()
52 writel(0x4F000000, CPG_PLL3CR); in blanche_init_sys()
56 writel(0xA5A5A500, &rwdt->rwtcsra); in blanche_init_sys()
57 writel(0xA5A5A500, &swdt->swtcsra); in blanche_init_sys()
63 { 0x0004, 0x0bffffff }, in blanche_init_pfc()
64 { 0x0008, 0x002fffff }, in blanche_init_pfc()
65 { 0x0014, 0x00000fff }, in blanche_init_pfc()
[all …]
/openbmc/qemu/hw/audio/
H A Dhda-codec-common.h28 #define QEMU_HDA_ID_OUTPUT ((QEMU_HDA_ID_VENDOR << 16) | 0x12)
29 #define QEMU_HDA_ID_DUPLEX ((QEMU_HDA_ID_VENDOR << 16) | 0x22)
30 #define QEMU_HDA_ID_MICRO ((QEMU_HDA_ID_VENDOR << 16) | 0x32)
37 #define QEMU_HDA_ID_OUTPUT ((QEMU_HDA_ID_VENDOR << 16) | 0x11)
38 #define QEMU_HDA_ID_DUPLEX ((QEMU_HDA_ID_VENDOR << 16) | 0x21)
39 #define QEMU_HDA_ID_MICRO ((QEMU_HDA_ID_VENDOR << 16) | 0x31)
146 .val = 0x00100101,
149 .val = 0x00010001,
163 .val = 0x00020002,
178 .val = 0,
[all …]
/openbmc/u-boot/board/renesas/gose/
H A Dgose_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/koelsch/
H A Dkoelsch_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait()
39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait()
48 u32 r0 = 0; in spl_init_sys()
50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/lager/
H A Dlager_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/stout/
H A Dstout_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait()
39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait()
48 u32 r0 = 0; in spl_init_sys()
50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/porter/
H A Dporter_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait()
39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait()
48 u32 r0 = 0; in spl_init_sys()
50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dtable.c7 0x01c, 0x07000000,
8 0x800, 0x00040000,
9 0x804, 0x00008003,
10 0x808, 0x0000fc00,
11 0x80c, 0x0000000a,
12 0x810, 0x10005088,
13 0x814, 0x020c3d10,
14 0x818, 0x00200185,
15 0x81c, 0x00000000,
16 0x820, 0x01000000,
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
85 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
[all …]
/openbmc/linux/include/uapi/scsi/fc/
H A Dfc_els.h20 * ELS Command codes - byte 0 of the frame payload
23 ELS_LS_RJT = 0x01, /* ESL reject */
24 ELS_LS_ACC = 0x02, /* ESL Accept */
25 ELS_PLOGI = 0x03, /* N_Port login */
26 ELS_FLOGI = 0x04, /* F_Port login */
27 ELS_LOGO = 0x05, /* Logout */
28 ELS_ABTX = 0x06, /* Abort exchange - obsolete */
29 ELS_RCS = 0x07, /* read connection status */
30 ELS_RES = 0x08, /* read exchange status block */
31 ELS_RSS = 0x09, /* read sequence status block */
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dps3av.h13 #define PS3AV_VERSION 0x205 /* version of ps3av command */
15 #define PS3AV_CID_AV_INIT 0x00000001
16 #define PS3AV_CID_AV_FIN 0x00000002
17 #define PS3AV_CID_AV_GET_HW_CONF 0x00000003
18 #define PS3AV_CID_AV_GET_MONITOR_INFO 0x00000004
19 #define PS3AV_CID_AV_ENABLE_EVENT 0x00000006
20 #define PS3AV_CID_AV_DISABLE_EVENT 0x00000007
21 #define PS3AV_CID_AV_TV_MUTE 0x0000000a
23 #define PS3AV_CID_AV_VIDEO_CS 0x00010001
24 #define PS3AV_CID_AV_VIDEO_MUTE 0x00010002
[all …]
/openbmc/linux/drivers/media/pci/cx23885/
H A Dcx23885-cards.c39 "\t\t Default: 0 [Disabled]");
48 .clk_freq = 0,
51 .vmux = 0,
68 .vmux = 0,
69 .gpio0 = 0xff00,
72 .vmux = 0,
73 .gpio0 = 0xff01,
77 .gpio0 = 0xff02,
81 .gpio0 = 0xff02,
90 .tuner_addr = 0x42, /* 0x84 >> 1 */
[all …]

12