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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_0_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
H A Dsdma0_4_1_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_default.h26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dtest_vminh.S4 * The minimum between 0x0002000300010005 and 0x0003000200020007 is
5 * 0x0003000300020007.
7 * input: r1 = 0x00010003 r0 = 0x00010005 r3 = 0x00030002 r2 = 0x00020007
8 * output: r1 = 0x00010002 r0 = 0x00010005
24 r1:0 = vminh(r1:0, r3:2)
/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r2_dps_w_ph.c10 rs = 0x00FF00FF; in main()
11 rt = 0x00010002; in main()
12 resulth = 0x04; in main()
13 resultl = 0xFFFFFD08; in main()
15 ("mthi %0, $ac1\n\t" in main()
18 "mfhi %0, $ac1\n\t" in main()
27 rs = 0xFFFF00FF; in main()
28 rt = 0xFFFF0002; in main()
29 resulth = 0x05; in main()
30 resultl = 0xFFFFFE08; in main()
[all …]
H A Dtest_dsp_r2_dpax_w_ph.c10 rs = 0x00FF00FF; in main()
11 rt = 0x00010002; in main()
12 resulth = 0x05; in main()
13 resultl = 0x0302; in main()
15 ("mthi %0, $ac1\n\t" in main()
18 "mfhi %0, $ac1\n\t" in main()
27 rs = 0xFFFF00FF; in main()
28 rt = 0xFFFF0002; in main()
29 resulth = 0x05; in main()
30 resultl = 0xFFFFFF06; in main()
[all …]
H A Dtest_dsp_r2_dpa_w_ph.c10 rs = 0x00FF00FF; in main()
11 rt = 0x00010002; in main()
12 resulth = 0x05; in main()
13 resultl = 0x0302; in main()
15 ("mthi %0, $ac1\n\t" in main()
18 "mfhi %0, $ac1\n\t" in main()
27 rs = 0xFFFF00FF; in main()
28 rt = 0xFFFF0002; in main()
29 resulth = 0x06; in main()
30 resultl = 0x206; in main()
[all …]
H A Dtest_dsp_r2_dpaqx_sa_w_ph.c10 ach = 0x00000005; in main()
11 acl = 0x00000005; in main()
12 rs = 0x00FF00FF; in main()
13 rt = 0x00010002; in main()
14 resulth = 0x00; in main()
15 resultl = 0x7FFFFFFF; in main()
16 resultdsp = 0x01; in main()
17 dsp = 0; in main()
20 "mthi %0, $ac1\n\t" in main()
23 "mfhi %0, $ac1\n\t" in main()
[all …]
H A Dtest_dsp_r2_dpaqx_s_w_ph.c10 rs = 0x800000FF; in main()
11 rt = 0x00018000; in main()
12 resulth = 0x05; in main()
13 resultl = 0x80000202; in main()
14 resultdsp = 0x01; in main()
16 ("mthi %0, $ac1\n\t" in main()
19 "mfhi %0, $ac1\n\t" in main()
25 dsp = (dsp >> 17) & 0x01; in main()
32 rs = 0x00FF00FF; in main()
33 rt = 0x00010002; in main()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/openbmc/qemu/include/hw/arm/
H A Draspberrypi-fw-defs.h15 RPI_FWREQ_PROPERTY_END = 0,
16 RPI_FWREQ_GET_FIRMWARE_REVISION = 0x00000001,
17 RPI_FWREQ_GET_FIRMWARE_VARIANT = 0x00000002,
18 RPI_FWREQ_GET_FIRMWARE_HASH = 0x00000003,
20 RPI_FWREQ_SET_CURSOR_INFO = 0x00008010,
21 RPI_FWREQ_SET_CURSOR_STATE = 0x00008011,
23 RPI_FWREQ_GET_BOARD_MODEL = 0x00010001,
24 RPI_FWREQ_GET_BOARD_REVISION = 0x00010002,
25 RPI_FWREQ_GET_BOARD_MAC_ADDRESS = 0x00010003,
26 RPI_FWREQ_GET_BOARD_SERIAL = 0x00010004,
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear300-evb.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
77 cd-gpios = <&gpio1 0 0>;
88 reg = <0xf8000000 0x800000>;
91 partition@0 {
93 reg = <0x0 0x10000>;
97 reg = <0x10000 0x50000>;
101 reg = <0x60000 0x10000>;
105 reg = <0x70000 0x10000>;
109 reg = <0x80000 0x310000>;
[all …]
H A Dspear1310-evb.dts18 reg = <0 0x40000000>;
24 pinctrl-0 = <&state_default>;
122 partition@0 {
124 reg = <0x0 0x80000>;
128 reg = <0x80000 0x140000>;
132 reg = <0x1C0000 0x40000>;
136 reg = <0x200000 0x40000>;
140 reg = <0x240000 0xC00000>;
144 reg = <0xE40000 0x0>;
151 #size-cells = <0>;
[all …]
H A Dspear1340-evb.dts18 reg = <0 0x40000000>;
24 pinctrl-0 = <&state_default>;
134 partition@0 {
136 reg = <0x0 0x200000>;
140 reg = <0x200000 0x200000>;
144 reg = <0x400000 0x100000>;
148 reg = <0x500000 0x100000>;
152 reg = <0x600000 0xC00000>;
156 reg = <0x1200000 0x0>;
176 reg = <0xe6000000 0x800000>;
[all …]
/openbmc/linux/sound/pci/ice1712/
H A Dhoontech.h19 #define ICE1712_SUBDEVICE_STDSP24 0x12141217 /* Hoontech SoundTrack Audio DSP 24 */
20 #define ICE1712_SUBDEVICE_STDSP24_VALUE 0x00010010 /* A dummy id for Hoontech SoundTrack Audio DSP…
21 #define ICE1712_SUBDEVICE_STDSP24_MEDIA7_1 0x16141217 /* Hoontech ST Audio DSP24 Media 7.1 */
22 #define ICE1712_SUBDEVICE_EVENT_EZ8 0x00010001 /* A dummy id for EZ8 */
23 #define ICE1712_SUBDEVICE_STAUDIO_ADCIII 0x00010002 /* A dummy id for STAudio ADCIII */
30 #define ICE1712_STDSP24_0_BOX(r, x) r[0] = ((r[0] & ~3) | ((x)&3))
31 #define ICE1712_STDSP24_0_DAREAR(r, x) r[0] = ((r[0] & ~4) | (((x)&1)<<2))
41 #define ICE1712_STDSP24_SET_ADDR(r, a) r[a&3] = ((r[a&3] & ~0x18) | (((a)&3)<<3))
42 #define ICE1712_STDSP24_CLOCK(r, a, c) r[a&3] = ((r[a&3] & ~0x20) | (((c)&1)<<5))
47 #define ICE1712_STDSP24_DAREAR (1<<0)
[all …]
/openbmc/linux/include/linux/platform_data/x86/
H A Dasus-wmi.h9 #define ASUS_WMI_METHODID_SPEC 0x43455053 /* BIOS SPECification */
10 #define ASUS_WMI_METHODID_SFBD 0x44424653 /* Set First Boot Device */
11 #define ASUS_WMI_METHODID_GLCD 0x44434C47 /* Get LCD status */
12 #define ASUS_WMI_METHODID_GPID 0x44495047 /* Get Panel ID?? (Resol) */
13 #define ASUS_WMI_METHODID_QMOD 0x444F4D51 /* Quiet MODe */
14 #define ASUS_WMI_METHODID_SPLV 0x4C425053 /* Set Panel Light Value */
15 #define ASUS_WMI_METHODID_AGFN 0x4E464741 /* Atk Generic FuNction */
16 #define ASUS_WMI_METHODID_SFUN 0x4E554653 /* FUNCtionalities */
17 #define ASUS_WMI_METHODID_SDSP 0x50534453 /* Set DiSPlay output */
18 #define ASUS_WMI_METHODID_GDSP 0x50534447 /* Get DiSPlay output */
[all …]
/openbmc/linux/include/soc/bcm2835/
H A Draspberrypi-firmware.h15 RPI_FIRMWARE_STATUS_REQUEST = 0,
16 RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000,
17 RPI_FIRMWARE_STATUS_ERROR = 0x80000001,
37 RPI_FIRMWARE_PROPERTY_END = 0,
38 RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001,
40 RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010,
41 RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011,
43 RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001,
44 RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002,
45 RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003,
[all …]
/openbmc/qemu/hw/scsi/
H A Dsrp.h45 SRP_LOGIN_REQ = 0x00,
46 SRP_TSK_MGMT = 0x01,
47 SRP_CMD = 0x02,
48 SRP_I_LOGOUT = 0x03,
49 SRP_LOGIN_RSP = 0xc0,
50 SRP_RSP = 0xc1,
51 SRP_LOGIN_REJ = 0xc2,
52 SRP_T_LOGOUT = 0x80,
53 SRP_CRED_REQ = 0x81,
54 SRP_AER_REQ = 0x82,
[all …]
/openbmc/linux/include/scsi/
H A Dsrp.h48 SRP_LOGIN_REQ = 0x00,
49 SRP_TSK_MGMT = 0x01,
50 SRP_CMD = 0x02,
51 SRP_I_LOGOUT = 0x03,
52 SRP_LOGIN_RSP = 0xc0,
53 SRP_RSP = 0xc1,
54 SRP_LOGIN_REJ = 0xc2,
55 SRP_T_LOGOUT = 0x80,
56 SRP_CRED_REQ = 0x81,
57 SRP_AER_REQ = 0x82,
[all …]
/openbmc/linux/include/linux/
H A Drndis.h8 #define RNDIS_MAJOR_VERSION 0x00000001
9 #define RNDIS_MINOR_VERSION 0x00000000
12 #define RNDIS_DF_CONNECTIONLESS 0x00000001U
13 #define RNDIS_DF_CONNECTION_ORIENTED 0x00000002U
14 #define RNDIS_DF_RAW_DATA 0x00000004U
21 #define RNDIS_MSG_COMPLETION 0x80000000
22 #define RNDIS_MSG_PACKET 0x00000001 /* 1-N packets */
23 #define RNDIS_MSG_INIT 0x00000002
25 #define RNDIS_MSG_HALT 0x00000003
26 #define RNDIS_MSG_QUERY 0x00000004
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
/openbmc/u-boot/arch/arm/mach-bcm283x/include/mach/
H A Dmbox.h41 #define BCM2835_MBOX_PHYSADDR 0x3f00b880
43 #define BCM2835_MBOX_PHYSADDR 0x2000b880
54 #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
55 #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000
58 #define BCM2835_CHAN_MASK 0xf
74 #define BCM2835_MBOX_REQ_CODE 0
75 #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000
78 memset((_m_), 0, sizeof(*(_m_))); \
80 (_m_)->hdr.code = 0; \
81 (_m_)->end_tag = 0; \
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8mq.dtsi47 reg = <0x00000000 0x40000000 0 0xc0000000>;
52 reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
53 <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
82 reg = <0x0 0x30670000 0x0 0x10000>;
93 reg = <0x0 0x30200000 0x0 0x10000>;
104 reg = <0x0 0x30210000 0x0 0x10000>;
115 reg = <0x0 0x30220000 0x0 0x10000>;
126 reg = <0x0 0x30230000 0x0 0x10000>;
137 reg = <0x0 0x30240000 0x0 0x10000>;
148 reg = <0x0 0x30260000 0x0 0x10000>;
[all …]
H A Drk3399-sdram-ddr3-1866.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80181219
18 0x17050a03
[all …]
H A Drk3399-sdram-ddr3-1333.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80120e12
18 0x11030802
[all …]

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