| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | mpic.h | 14 #define MPIC_GREG_BASE 0x01000
16 #define MPIC_GREG_FEATURE_0 0x00000
17 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
19 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
21 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
22 #define MPIC_GREG_FEATURE_1 0x00010
23 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
24 #define MPIC_GREG_GCONF_RESET 0x80000000
27 * 0b00 = pass through (interrupts routed to IRQ0)
28 * 0b01 = Mixed mode
[all …]
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| /openbmc/linux/arch/parisc/include/uapi/asm/ |
| H A D | termbits.h | 42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
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| /openbmc/linux/include/uapi/asm-generic/ |
| H A D | termbits.h | 42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/amd/ |
| H A D | amd-seattle-xgbe-b.dtsi | 10 #clock-cells = <0>;
17 #clock-cells = <0>;
24 #clock-cells = <0>;
31 #clock-cells = <0>;
38 reg = <0 0xe0700000 0 0x80000>,
39 <0 0xe0780000 0 0x80000>,
40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
43 interrupts = <0 325 4>,
[all …]
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| /openbmc/linux/arch/x86/events/ |
| H A D | perf_event_flags.h | 5 PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
6 PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
7 PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
8 PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
9 PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
10 PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
11 PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
12 /* 0x00080 */
13 PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
14 PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
[all …]
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| /openbmc/linux/arch/mips/include/uapi/asm/ |
| H A D | termbits.h | 55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
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| /openbmc/linux/arch/powerpc/include/asm/nohash/32/ |
| H A D | pte-85xx.h | 12 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
20 #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
21 #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
22 #define _PAGE_RW 0x00004 /* S: Write permission (SW) */
23 #define _PAGE_DIRTY 0x00008 /* S: Page dirty */
24 #define _PAGE_EXEC 0x00010 /* H: SX permission */
25 #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
27 #define _PAGE_ENDIAN 0x00040 /* H: E bit */
28 #define _PAGE_GUARDED 0x00080 /* H: G bit */
29 #define _PAGE_COHERENT 0x00100 /* H: M bit */
[all …]
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| /openbmc/linux/drivers/gpu/drm/arm/ |
| H A D | malidp_regs.h | 20 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
34 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
50 #define MALIDP550_SE_IRQ_EOW (1 << 0)
54 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
67 #define MALIDP_CFG_VALID (1 << 0)
68 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)
75 #define MALIDP_REG_STATUS 0x00000
76 #define MALIDP_REG_SETIRQ 0x00004
77 #define MALIDP_REG_MASKIRQ 0x00008
78 #define MALIDP_REG_CLEARIRQ 0x0000c
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | amd-xgbe.txt | 32 0 - 1GbE and 10GbE (default)
44 0 - Off
55 reg = <0 0xe0700000 0 0x80000>,
56 <0 0xe0780000 0 0x80000>,
57 <0 0xe1240800 0 0x00400>,
58 <0 0xe1250000 0 0x00060>,
59 <0 0xe1250080 0 0x00004>;
61 interrupts = <0 325 4>,
62 <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
63 <0 323 4>;
[all …]
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| /openbmc/linux/arch/powerpc/include/uapi/asm/ |
| H A D | termbits.h | 48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]
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| /openbmc/linux/arch/alpha/include/uapi/asm/ |
| H A D | termbits.h | 54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
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| /openbmc/qemu/target/ppc/ |
| H A D | mmu-hash64.h | 27 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
28 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
34 #define SLB_VSID_B 0xc000000000000000ULL
35 #define SLB_VSID_B_256M 0x0000000000000000ULL
36 #define SLB_VSID_B_1T 0x4000000000000000ULL
37 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
38 #define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
40 #define SLB_VSID_KS 0x0000000000000800ULL
41 #define SLB_VSID_KP 0x0000000000000400ULL
42 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
[all …]
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| H A D | vmmnv04.c | 31 u32 data = addr | 0x00000003; /* PRESENT, RW. */ in nv04_vmm_pgt_pte()
34 data += 0x00001000; in nv04_vmm_pgt_pte()
52 VMM_WO032(pt, vmm, 8 + (ptei++ * 4), *map->dma++ | 0x00000003); in nv04_vmm_pgt_dma()
63 VMM_FO032(pt, vmm, 8 + (ptei * 4), 0, ptes); in nv04_vmm_pgt_unmap()
75 { PGT, 15, 4, 0x1000, &nv04_vmm_desc_pgt },
96 { 12, &nv04_vmm_desc_12[0], NVKM_VMM_PAGE_HOST },
135 mem = vmm->pd->pt[0]->memory; in nv04_vmm_new()
137 nvkm_wo32(mem, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ in nv04_vmm_new()
138 nvkm_wo32(mem, 0x00004, vmm->limit - 1); in nv04_vmm_new()
140 return 0; in nv04_vmm_new()
|
| /openbmc/linux/drivers/gpu/drm/v3d/ |
| H A D | v3d_regs.h | 14 WARN_ON((fieldval & ~field##_MASK) != 0); \
23 #define V3D_HUB_AXICFG 0x00000
24 # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0)
25 # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0
26 #define V3D_HUB_UIFCFG 0x00004
27 #define V3D_HUB_IDENT0 0x00008
29 #define V3D_HUB_IDENT1 0x0000c
40 # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0)
41 # define V3D_HUB_IDENT1_TVER_SHIFT 0
43 #define V3D_HUB_IDENT2 0x00010
[all …]
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| /openbmc/linux/arch/sparc/include/uapi/asm/ |
| H A D | termbits.h | 51 #define VINTR 0
78 #define IUCLC 0x0200
79 #define IXON 0x0400
80 #define IXOFF 0x1000
81 #define IMAXBEL 0x2000
82 #define IUTF8 0x4000
85 #define OLCUC 0x00002
86 #define ONLCR 0x00004
87 #define NLDLY 0x00100
88 #define NL0 0x00000
[all …]
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| /openbmc/linux/include/linux/perf/ |
| H A D | arm_pmu.h | 27 #define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */
28 #define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */
29 #define ARMPMU_EVT_63BIT 0x00004 /* Event uses a 63bit counter */
35 #define HW_OP_UNSUPPORTED 0xFFFF
37 #define CACHE_OP_UNSUPPORTED 0xFFFF
40 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
43 [0 ... C(MAX) - 1] = { \
44 [0 ... C(OP_MAX) - 1] = { \
45 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
58 * an event. A 0 means that the counter can be used.
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/ti-common/ |
| H A D | keystone_net.h | 18 #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000)
19 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900)
20 #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300)
21 #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100)
22 #define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
25 #define CPGMACSL_REG_CTL 0x04
26 #define CPGMACSL_REG_STATUS 0x08
27 #define CPGMACSL_REG_RESET 0x0c
28 #define CPGMACSL_REG_MAXLEN 0x10
32 #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000)
[all …]
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| /openbmc/u-boot/include/asm-generic/ |
| H A D | global_data.h | 142 #define gd_board_type() 0
148 #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
149 #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
150 #define GD_FLG_SILENT 0x00004 /* Silent mode */
151 #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
152 #define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
153 #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
154 #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
155 #define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */
156 #define GD_FLG_SERIAL_READY 0x00100 /* Pre-reloc serial console ready */
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/perf/ |
| H A D | riscv,pmu.yaml | 78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
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| /openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | hdmi5_core.h | 16 #define HDMI_CORE_DESIGN_ID 0x00000
17 #define HDMI_CORE_REVISION_ID 0x00004
18 #define HDMI_CORE_PRODUCT_ID0 0x00008
19 #define HDMI_CORE_PRODUCT_ID1 0x0000C
20 #define HDMI_CORE_CONFIG0_ID 0x00010
21 #define HDMI_CORE_CONFIG1_ID 0x00014
22 #define HDMI_CORE_CONFIG2_ID 0x00018
23 #define HDMI_CORE_CONFIG3_ID 0x0001C
26 #define HDMI_CORE_IH_FC_STAT0 0x00400
27 #define HDMI_CORE_IH_FC_STAT1 0x00404
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| /openbmc/linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | hdmi5_core.h | 16 #define HDMI_CORE_DESIGN_ID 0x00000
17 #define HDMI_CORE_REVISION_ID 0x00004
18 #define HDMI_CORE_PRODUCT_ID0 0x00008
19 #define HDMI_CORE_PRODUCT_ID1 0x0000C
20 #define HDMI_CORE_CONFIG0_ID 0x00010
21 #define HDMI_CORE_CONFIG1_ID 0x00014
22 #define HDMI_CORE_CONFIG2_ID 0x00018
23 #define HDMI_CORE_CONFIG3_ID 0x0001C
26 #define HDMI_CORE_IH_FC_STAT0 0x00400
27 #define HDMI_CORE_IH_FC_STAT1 0x00404
[all …]
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| /openbmc/u-boot/drivers/video/ |
| H A D | logicore_dp_dpcd.h | 16 #define DPCD_REV 0x00000
17 #define DPCD_MAX_LINK_RATE 0x00001
18 #define DPCD_MAX_LANE_COUNT 0x00002
19 #define DPCD_MAX_DOWNSPREAD 0x00003
20 #define DPCD_NORP_PWR_V_CAP 0x00004
21 #define DPCD_DOWNSP_PRESENT 0x00005
22 #define DPCD_ML_CH_CODING_CAP 0x00006
23 #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
24 #define DPCD_RX_PORT0_CAP_0 0x00008
25 #define DPCD_RX_PORT0_CAP_1 0x00009
[all …]
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| /openbmc/linux/drivers/usb/gadget/udc/ |
| H A D | goku_udc.h | 12 * PCI BAR 0 points to these registers.
16 u32 int_status; /* 0x000 */
18 #define INT_SUSPEND 0x00001 /* or resume */
19 #define INT_USBRESET 0x00002
20 #define INT_ENDPOINT0 0x00004
21 #define INT_SETUP 0x00008
22 #define INT_STATUS 0x00010
23 #define INT_STATUSNAK 0x00020
24 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
25 # define INT_EP1DATASET 0x00040
[all …]
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| /openbmc/linux/drivers/scsi/ibmvscsi_tgt/ |
| H A D | ibmvscsi_tgt.h | 27 #define MSG_HI 0
36 #define SRP_VIOLATION 0x102 /* general error code */
55 #define LOCAL 0
70 #define ADAPT_SUCCESS 0L
139 SCSI_CDB = 0x01,
140 TASK_MANAGEMENT = 0x02,
141 /* MAD or addressed to port 0 */
142 ADAPTER_MAD = 0x04,
143 UNSET_TYPE = 0x08,
166 #define CMD_FAST_FAIL BIT(0)
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| /openbmc/linux/drivers/net/wireless/realtek/rtw89/ |
| H A D | rtw8851b_rfk_table.c | 8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
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