1e559355aSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ad49f860SLiviu Dudau /* 3ad49f860SLiviu Dudau * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. 4ad49f860SLiviu Dudau * Author: Liviu Dudau <Liviu.Dudau@arm.com> 5ad49f860SLiviu Dudau * 6ad49f860SLiviu Dudau * ARM Mali DP500/DP550/DP650 registers definition. 7ad49f860SLiviu Dudau */ 8ad49f860SLiviu Dudau 9ad49f860SLiviu Dudau #ifndef __MALIDP_REGS_H__ 10ad49f860SLiviu Dudau #define __MALIDP_REGS_H__ 11ad49f860SLiviu Dudau 12ad49f860SLiviu Dudau /* 13ad49f860SLiviu Dudau * abbreviations used: 14ad49f860SLiviu Dudau * - DC - display core (general settings) 15ad49f860SLiviu Dudau * - DE - display engine 16ad49f860SLiviu Dudau * - SE - scaling engine 17ad49f860SLiviu Dudau */ 18ad49f860SLiviu Dudau 19ad49f860SLiviu Dudau /* interrupt bit masks */ 20ad49f860SLiviu Dudau #define MALIDP_DE_IRQ_UNDERRUN (1 << 0) 21ad49f860SLiviu Dudau 22ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_AXI_ERR (1 << 4) 23ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_VSYNC (1 << 5) 24ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_PROG_LINE (1 << 6) 25ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_SATURATION (1 << 7) 26ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_VALID (1 << 8) 27ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_MODE (1 << 11) 28ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_CONF_ACTIVE (1 << 17) 29ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_PM_ACTIVE (1 << 18) 30ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_TESTMODE_ACTIVE (1 << 19) 31ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE (1 << 24) 32ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_AXI_BUSY (1 << 28) 33ad49f860SLiviu Dudau #define MALIDP500_DE_IRQ_GLOBAL (1 << 31) 34ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0) 35ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_VALID (1 << 4) 36ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_INIT_BUSY (1 << 5) 37ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_AXI_ERROR (1 << 8) 38ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_OVERRUN (1 << 9) 39ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PROG_LINE1 (1 << 12) 40ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PROG_LINE2 (1 << 13) 41ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_CONF_ACTIVE (1 << 17) 42ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_PM_ACTIVE (1 << 18) 43ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_AXI_BUSY (1 << 28) 44ad49f860SLiviu Dudau #define MALIDP500_SE_IRQ_GLOBAL (1 << 31) 45ad49f860SLiviu Dudau 46ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_SATURATION (1 << 8) 47ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_VSYNC (1 << 12) 48ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_PROG_LINE (1 << 13) 49ad49f860SLiviu Dudau #define MALIDP550_DE_IRQ_AXI_ERR (1 << 16) 50ad49f860SLiviu Dudau #define MALIDP550_SE_IRQ_EOW (1 << 0) 51ad49f860SLiviu Dudau #define MALIDP550_SE_IRQ_AXI_ERR (1 << 16) 52613c5c7fSAlexandru Gheorghe #define MALIDP550_SE_IRQ_OVR (1 << 17) 53613c5c7fSAlexandru Gheorghe #define MALIDP550_SE_IRQ_IBSY (1 << 18) 54ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0) 55ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_MODE (1 << 4) 56ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16) 57ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_DE (1 << 20) 58ad49f860SLiviu Dudau #define MALIDP550_DC_IRQ_SE (1 << 24) 59ad49f860SLiviu Dudau 60ad49f860SLiviu Dudau #define MALIDP650_DE_IRQ_DRIFT (1 << 4) 61613c5c7fSAlexandru Gheorghe #define MALIDP650_DE_IRQ_ACEV1 (1 << 17) 62613c5c7fSAlexandru Gheorghe #define MALIDP650_DE_IRQ_ACEV2 (1 << 18) 63613c5c7fSAlexandru Gheorghe #define MALIDP650_DE_IRQ_ACEG (1 << 19) 64613c5c7fSAlexandru Gheorghe #define MALIDP650_DE_IRQ_AXIEP (1 << 28) 65ad49f860SLiviu Dudau 66ad49f860SLiviu Dudau /* bit masks that are common between products */ 67ad49f860SLiviu Dudau #define MALIDP_CFG_VALID (1 << 0) 6802725d31SMihail Atanassov #define MALIDP_DISP_FUNC_GAMMA (1 << 0) 696954f245SMihail Atanassov #define MALIDP_DISP_FUNC_CADJ (1 << 4) 70ad49f860SLiviu Dudau #define MALIDP_DISP_FUNC_ILACED (1 << 8) 71846c87a0SLiviu Dudau #define MALIDP_SCALE_ENGINE_EN (1 << 16) 72846c87a0SLiviu Dudau #define MALIDP_SE_MEMWRITE_EN (2 << 5) 73ad49f860SLiviu Dudau 74ad49f860SLiviu Dudau /* register offsets for IRQ management */ 75ad49f860SLiviu Dudau #define MALIDP_REG_STATUS 0x00000 76ad49f860SLiviu Dudau #define MALIDP_REG_SETIRQ 0x00004 77ad49f860SLiviu Dudau #define MALIDP_REG_MASKIRQ 0x00008 78ad49f860SLiviu Dudau #define MALIDP_REG_CLEARIRQ 0x0000c 79ad49f860SLiviu Dudau 80ad49f860SLiviu Dudau /* register offsets */ 81ad49f860SLiviu Dudau #define MALIDP_DE_CORE_ID 0x00018 82ad49f860SLiviu Dudau #define MALIDP_DE_DISPLAY_FUNC 0x00020 83ad49f860SLiviu Dudau 84ad49f860SLiviu Dudau /* these offsets are relative to MALIDP5x0_TIMINGS_BASE */ 85ad49f860SLiviu Dudau #define MALIDP_DE_H_TIMINGS 0x0 86ad49f860SLiviu Dudau #define MALIDP_DE_V_TIMINGS 0x4 87ad49f860SLiviu Dudau #define MALIDP_DE_SYNC_WIDTH 0x8 88ad49f860SLiviu Dudau #define MALIDP_DE_HV_ACTIVE 0xc 89ad49f860SLiviu Dudau 9083d642eeSMihail Atanassov /* Stride register offsets relative to Lx_BASE */ 9183d642eeSMihail Atanassov #define MALIDP_DE_LG_STRIDE 0x18 9283d642eeSMihail Atanassov #define MALIDP_DE_LV_STRIDE0 0x18 93d1479f61SMihail Atanassov #define MALIDP550_DE_LS_R1_STRIDE 0x28 9483d642eeSMihail Atanassov 95ad49f860SLiviu Dudau /* macros to set values into registers */ 96ad49f860SLiviu Dudau #define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0) 97ad49f860SLiviu Dudau #define MALIDP_DE_H_BACKPORCH(x) (((x) & 0x3ff) << 16) 98ad49f860SLiviu Dudau #define MALIDP500_DE_V_FRONTPORCH(x) (((x) & 0xff) << 0) 99ad49f860SLiviu Dudau #define MALIDP550_DE_V_FRONTPORCH(x) (((x) & 0xfff) << 0) 100ad49f860SLiviu Dudau #define MALIDP_DE_V_BACKPORCH(x) (((x) & 0xff) << 16) 101ad49f860SLiviu Dudau #define MALIDP_DE_H_SYNCWIDTH(x) (((x) & 0x3ff) << 0) 102ad49f860SLiviu Dudau #define MALIDP_DE_V_SYNCWIDTH(x) (((x) & 0xff) << 16) 103ad49f860SLiviu Dudau #define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0) 104ad49f860SLiviu Dudau #define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16) 105ad49f860SLiviu Dudau 106592d8c8cSMihail Atanassov #define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16) 107592d8c8cSMihail Atanassov 10802725d31SMihail Atanassov /* register offsets relative to MALIDP5x0_COEFFS_BASE */ 10902725d31SMihail Atanassov #define MALIDP_COLOR_ADJ_COEF 0x00000 11002725d31SMihail Atanassov #define MALIDP_COEF_TABLE_ADDR 0x00030 11102725d31SMihail Atanassov #define MALIDP_COEF_TABLE_DATA 0x00034 11202725d31SMihail Atanassov 11328ce675bSMihail Atanassov /* Scaling engine registers and masks. */ 11428ce675bSMihail Atanassov #define MALIDP_SE_SCALING_EN (1 << 0) 11528ce675bSMihail Atanassov #define MALIDP_SE_ALPHA_EN (1 << 1) 1160274e6a0SMihail Atanassov #define MALIDP_SE_ENH_MASK 3 1170274e6a0SMihail Atanassov #define MALIDP_SE_ENH(x) (((x) & MALIDP_SE_ENH_MASK) << 2) 11828ce675bSMihail Atanassov #define MALIDP_SE_RGBO_IF_EN (1 << 4) 11928ce675bSMihail Atanassov #define MALIDP550_SE_CTL_SEL_MASK 7 12028ce675bSMihail Atanassov #define MALIDP550_SE_CTL_VCSEL(x) \ 12128ce675bSMihail Atanassov (((x) & MALIDP550_SE_CTL_SEL_MASK) << 20) 12228ce675bSMihail Atanassov #define MALIDP550_SE_CTL_HCSEL(x) \ 12328ce675bSMihail Atanassov (((x) & MALIDP550_SE_CTL_SEL_MASK) << 16) 12428ce675bSMihail Atanassov 12528ce675bSMihail Atanassov /* Blocks with offsets from SE_CONTROL register. */ 12628ce675bSMihail Atanassov #define MALIDP_SE_LAYER_CONTROL 0x14 12728ce675bSMihail Atanassov #define MALIDP_SE_L0_IN_SIZE 0x00 12828ce675bSMihail Atanassov #define MALIDP_SE_L0_OUT_SIZE 0x04 12928ce675bSMihail Atanassov #define MALIDP_SE_SET_V_SIZE(x) (((x) & 0x1fff) << 16) 13028ce675bSMihail Atanassov #define MALIDP_SE_SET_H_SIZE(x) (((x) & 0x1fff) << 0) 13128ce675bSMihail Atanassov #define MALIDP_SE_SCALING_CONTROL 0x24 13228ce675bSMihail Atanassov #define MALIDP_SE_H_INIT_PH 0x00 13328ce675bSMihail Atanassov #define MALIDP_SE_H_DELTA_PH 0x04 13428ce675bSMihail Atanassov #define MALIDP_SE_V_INIT_PH 0x08 13528ce675bSMihail Atanassov #define MALIDP_SE_V_DELTA_PH 0x0c 13628ce675bSMihail Atanassov #define MALIDP_SE_COEFFTAB_ADDR 0x10 13728ce675bSMihail Atanassov #define MALIDP_SE_COEFFTAB_ADDR_MASK 0x7f 13828ce675bSMihail Atanassov #define MALIDP_SE_V_COEFFTAB (1 << 8) 13928ce675bSMihail Atanassov #define MALIDP_SE_H_COEFFTAB (1 << 9) 14028ce675bSMihail Atanassov #define MALIDP_SE_SET_V_COEFFTAB_ADDR(x) \ 14128ce675bSMihail Atanassov (MALIDP_SE_V_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK)) 14228ce675bSMihail Atanassov #define MALIDP_SE_SET_H_COEFFTAB_ADDR(x) \ 14328ce675bSMihail Atanassov (MALIDP_SE_H_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK)) 14428ce675bSMihail Atanassov #define MALIDP_SE_COEFFTAB_DATA 0x14 14528ce675bSMihail Atanassov #define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff 14628ce675bSMihail Atanassov #define MALIDP_SE_SET_COEFFTAB_DATA(x) \ 14728ce675bSMihail Atanassov ((x) & MALIDP_SE_COEFFTAB_DATA_MASK) 148*b62cc8faSpengfuyuan /* Enhance coefficients register offset */ 1490274e6a0SMihail Atanassov #define MALIDP_SE_IMAGE_ENH 0x3C 1500274e6a0SMihail Atanassov /* ENH_LIMITS offset 0x0 */ 1510274e6a0SMihail Atanassov #define MALIDP_SE_ENH_LOW_LEVEL 24 1520274e6a0SMihail Atanassov #define MALIDP_SE_ENH_HIGH_LEVEL 63 1530274e6a0SMihail Atanassov #define MALIDP_SE_ENH_LIMIT_MASK 0xfff 1540274e6a0SMihail Atanassov #define MALIDP_SE_SET_ENH_LIMIT_LOW(x) \ 1550274e6a0SMihail Atanassov ((x) & MALIDP_SE_ENH_LIMIT_MASK) 1560274e6a0SMihail Atanassov #define MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \ 1570274e6a0SMihail Atanassov (((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16) 1580274e6a0SMihail Atanassov #define MALIDP_SE_ENH_COEFF0 0x04 15928ce675bSMihail Atanassov 160846c87a0SLiviu Dudau 161846c87a0SLiviu Dudau /* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */ 162846c87a0SLiviu Dudau #define MALIDP_MW_FORMAT 0x00000 163846c87a0SLiviu Dudau #define MALIDP_MW_P1_STRIDE 0x00004 164846c87a0SLiviu Dudau #define MALIDP_MW_P2_STRIDE 0x00008 165846c87a0SLiviu Dudau #define MALIDP_MW_P1_PTR_LOW 0x0000c 166846c87a0SLiviu Dudau #define MALIDP_MW_P1_PTR_HIGH 0x00010 167846c87a0SLiviu Dudau #define MALIDP_MW_P2_PTR_LOW 0x0002c 168846c87a0SLiviu Dudau #define MALIDP_MW_P2_PTR_HIGH 0x00030 169846c87a0SLiviu Dudau 170ad49f860SLiviu Dudau /* register offsets and bits specific to DP500 */ 1714d6000edSMihail Atanassov #define MALIDP500_ADDR_SPACE_SIZE 0x01000 172ad49f860SLiviu Dudau #define MALIDP500_DC_BASE 0x00000 173ad49f860SLiviu Dudau #define MALIDP500_DC_CONTROL 0x0000c 174ad49f860SLiviu Dudau #define MALIDP500_DC_CONFIG_REQ (1 << 17) 175ad49f860SLiviu Dudau #define MALIDP500_HSYNCPOL (1 << 20) 176ad49f860SLiviu Dudau #define MALIDP500_VSYNCPOL (1 << 21) 177ad49f860SLiviu Dudau #define MALIDP500_DC_CLEAR_MASK 0x300fff 178ad49f860SLiviu Dudau #define MALIDP500_DE_LINE_COUNTER 0x00010 179ad49f860SLiviu Dudau #define MALIDP500_DE_AXI_CONTROL 0x00014 180ad49f860SLiviu Dudau #define MALIDP500_DE_SECURE_CTRL 0x0001c 181ad49f860SLiviu Dudau #define MALIDP500_DE_CHROMA_KEY 0x00024 182ad49f860SLiviu Dudau #define MALIDP500_TIMINGS_BASE 0x00028 183ad49f860SLiviu Dudau 184ad49f860SLiviu Dudau #define MALIDP500_CONFIG_3D 0x00038 185ad49f860SLiviu Dudau #define MALIDP500_BGND_COLOR 0x0003c 186ad49f860SLiviu Dudau #define MALIDP500_OUTPUT_DEPTH 0x00044 1876e810eb5SMihail Atanassov #define MALIDP500_COEFFS_BASE 0x00078 18802725d31SMihail Atanassov 18902725d31SMihail Atanassov /* 19002725d31SMihail Atanassov * The YUV2RGB coefficients on the DP500 are not in the video layer's register 19102725d31SMihail Atanassov * block. They belong in a separate block above the layer's registers, hence 19202725d31SMihail Atanassov * the negative offset. 19302725d31SMihail Atanassov */ 19402725d31SMihail Atanassov #define MALIDP500_LV_YUV2RGB ((s16)(-0xB8)) 195ad49f860SLiviu Dudau #define MALIDP500_DE_LV_BASE 0x00100 196ad49f860SLiviu Dudau #define MALIDP500_DE_LV_PTR_BASE 0x00124 19754b4260aSAyan Kumar Halder #define MALIDP500_DE_LV_AD_CTRL 0x00400 198ad49f860SLiviu Dudau #define MALIDP500_DE_LG1_BASE 0x00200 199ad49f860SLiviu Dudau #define MALIDP500_DE_LG1_PTR_BASE 0x0021c 20054b4260aSAyan Kumar Halder #define MALIDP500_DE_LG1_AD_CTRL 0x0040c 201ad49f860SLiviu Dudau #define MALIDP500_DE_LG2_BASE 0x00300 202ad49f860SLiviu Dudau #define MALIDP500_DE_LG2_PTR_BASE 0x0031c 20354b4260aSAyan Kumar Halder #define MALIDP500_DE_LG2_AD_CTRL 0x00418 204ad49f860SLiviu Dudau #define MALIDP500_SE_BASE 0x00c00 20528ce675bSMihail Atanassov #define MALIDP500_SE_CONTROL 0x00c0c 2061cb3cbe7SLiviu Dudau #define MALIDP500_SE_MEMWRITE_OUT_SIZE 0x00c2c 207b1150781SAlexandru Gheorghe #define MALIDP500_SE_RGB_YUV_COEFFS 0x00C74 2081cb3cbe7SLiviu Dudau #define MALIDP500_SE_MEMWRITE_BASE 0x00e00 209ad49f860SLiviu Dudau #define MALIDP500_DC_IRQ_BASE 0x00f00 210ad49f860SLiviu Dudau #define MALIDP500_CONFIG_VALID 0x00f00 211ad49f860SLiviu Dudau #define MALIDP500_CONFIG_ID 0x00fd4 212ad49f860SLiviu Dudau 213d298e6a2SWen He /* 214d298e6a2SWen He * The quality of service (QoS) register on the DP500. RQOS register values 215d298e6a2SWen He * are driven by the ARQOS signal, using AXI transacations, dependent on the 216d298e6a2SWen He * FIFO input level. 217d298e6a2SWen He * The RQOS register can also set QoS levels for: 218d298e6a2SWen He * - RED_ARQOS @ A 4-bit signal value for close to underflow conditions 219d298e6a2SWen He * - GREEN_ARQOS @ A 4-bit signal value for normal conditions 220d298e6a2SWen He */ 221d298e6a2SWen He #define MALIDP500_RQOS_QUALITY 0x00500 222d298e6a2SWen He 223ad49f860SLiviu Dudau /* register offsets and bits specific to DP550/DP650 */ 2244d6000edSMihail Atanassov #define MALIDP550_ADDR_SPACE_SIZE 0x10000 225ad49f860SLiviu Dudau #define MALIDP550_DE_CONTROL 0x00010 226ad49f860SLiviu Dudau #define MALIDP550_DE_LINE_COUNTER 0x00014 227ad49f860SLiviu Dudau #define MALIDP550_DE_AXI_CONTROL 0x00018 228ad49f860SLiviu Dudau #define MALIDP550_DE_QOS 0x0001c 229ad49f860SLiviu Dudau #define MALIDP550_TIMINGS_BASE 0x00030 230ad49f860SLiviu Dudau #define MALIDP550_HSYNCPOL (1 << 12) 231ad49f860SLiviu Dudau #define MALIDP550_VSYNCPOL (1 << 28) 232ad49f860SLiviu Dudau 233ad49f860SLiviu Dudau #define MALIDP550_DE_DISP_SIDEBAND 0x00040 234ad49f860SLiviu Dudau #define MALIDP550_DE_BGND_COLOR 0x00044 235ad49f860SLiviu Dudau #define MALIDP550_DE_OUTPUT_DEPTH 0x0004c 23602725d31SMihail Atanassov #define MALIDP550_COEFFS_BASE 0x00050 2376e810eb5SMihail Atanassov #define MALIDP550_LV_YUV2RGB 0x00084 238ad49f860SLiviu Dudau #define MALIDP550_DE_LV1_BASE 0x00100 239ad49f860SLiviu Dudau #define MALIDP550_DE_LV1_PTR_BASE 0x00124 24054b4260aSAyan Kumar Halder #define MALIDP550_DE_LV1_AD_CTRL 0x001B8 241ad49f860SLiviu Dudau #define MALIDP550_DE_LV2_BASE 0x00200 242ad49f860SLiviu Dudau #define MALIDP550_DE_LV2_PTR_BASE 0x00224 24354b4260aSAyan Kumar Halder #define MALIDP550_DE_LV2_AD_CTRL 0x002B8 244ad49f860SLiviu Dudau #define MALIDP550_DE_LG_BASE 0x00300 245ad49f860SLiviu Dudau #define MALIDP550_DE_LG_PTR_BASE 0x0031c 24654b4260aSAyan Kumar Halder #define MALIDP550_DE_LG_AD_CTRL 0x00330 247ad49f860SLiviu Dudau #define MALIDP550_DE_LS_BASE 0x00400 248ad49f860SLiviu Dudau #define MALIDP550_DE_LS_PTR_BASE 0x0042c 249ad49f860SLiviu Dudau #define MALIDP550_DE_PERF_BASE 0x00500 250ad49f860SLiviu Dudau #define MALIDP550_SE_BASE 0x08000 25128ce675bSMihail Atanassov #define MALIDP550_SE_CONTROL 0x08010 252846c87a0SLiviu Dudau #define MALIDP550_SE_MEMWRITE_ONESHOT (1 << 7) 253846c87a0SLiviu Dudau #define MALIDP550_SE_MEMWRITE_OUT_SIZE 0x08030 254b1150781SAlexandru Gheorghe #define MALIDP550_SE_RGB_YUV_COEFFS 0x08078 255846c87a0SLiviu Dudau #define MALIDP550_SE_MEMWRITE_BASE 0x08100 256ad49f860SLiviu Dudau #define MALIDP550_DC_BASE 0x0c000 257ad49f860SLiviu Dudau #define MALIDP550_DC_CONTROL 0x0c010 258ad49f860SLiviu Dudau #define MALIDP550_DC_CONFIG_REQ (1 << 16) 259ad49f860SLiviu Dudau #define MALIDP550_CONFIG_VALID 0x0c014 260ad49f860SLiviu Dudau #define MALIDP550_CONFIG_ID 0x0ffd4 261ad49f860SLiviu Dudau 2621f23a56aSJamie Fox /* register offsets specific to DP650 */ 2631f23a56aSJamie Fox #define MALIDP650_DE_LV_MMU_CTRL 0x000D0 2641f23a56aSJamie Fox #define MALIDP650_DE_LG_MMU_CTRL 0x00048 2651f23a56aSJamie Fox #define MALIDP650_DE_LS_MMU_CTRL 0x00078 2661f23a56aSJamie Fox 2671f23a56aSJamie Fox /* bit masks to set the MMU control register */ 2681f23a56aSJamie Fox #define MALIDP_MMU_CTRL_EN (1 << 0) 2691f23a56aSJamie Fox #define MALIDP_MMU_CTRL_MODE (1 << 4) 2701f23a56aSJamie Fox #define MALIDP_MMU_CTRL_PX_PS(x) (1 << (8 + (x))) 2711f23a56aSJamie Fox #define MALIDP_MMU_CTRL_PP_NUM_REQ(x) (((x) & 0x7f) << 12) 2721f23a56aSJamie Fox 27354b4260aSAyan Kumar Halder /* AFBC register offsets relative to MALIDPXXX_DE_LX_AD_CTRL */ 27454b4260aSAyan Kumar Halder /* The following register offsets are common for DP500, DP550 and DP650 */ 27554b4260aSAyan Kumar Halder #define MALIDP_AD_CROP_H 0x4 27654b4260aSAyan Kumar Halder #define MALIDP_AD_CROP_V 0x8 27754b4260aSAyan Kumar Halder #define MALIDP_AD_END_PTR_LOW 0xc 27854b4260aSAyan Kumar Halder #define MALIDP_AD_END_PTR_HIGH 0x10 27954b4260aSAyan Kumar Halder 28054b4260aSAyan Kumar Halder /* AFBC decoder Registers */ 28154b4260aSAyan Kumar Halder #define MALIDP_AD_EN BIT(0) 28254b4260aSAyan Kumar Halder #define MALIDP_AD_YTR BIT(4) 28354b4260aSAyan Kumar Halder #define MALIDP_AD_BS BIT(8) 28454b4260aSAyan Kumar Halder #define MALIDP_AD_CROP_RIGHT_OFFSET 16 28554b4260aSAyan Kumar Halder #define MALIDP_AD_CROP_BOTTOM_OFFSET 16 28654b4260aSAyan Kumar Halder 287ad49f860SLiviu Dudau /* 288ad49f860SLiviu Dudau * Starting with DP550 the register map blocks has been standardised to the 289ad49f860SLiviu Dudau * following layout: 290ad49f860SLiviu Dudau * 291ad49f860SLiviu Dudau * Offset Block registers 292ad49f860SLiviu Dudau * 0x00000 Display Engine 293ad49f860SLiviu Dudau * 0x08000 Scaling Engine 294ad49f860SLiviu Dudau * 0x0c000 Display Core 295ad49f860SLiviu Dudau * 0x10000 Secure control 296ad49f860SLiviu Dudau * 297ad49f860SLiviu Dudau * The old DP500 IP mixes some DC with the DE registers, hence the need 298ad49f860SLiviu Dudau * for a mapping structure. 299ad49f860SLiviu Dudau */ 300ad49f860SLiviu Dudau 301ad49f860SLiviu Dudau #endif /* __MALIDP_REGS_H__ */ 302