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/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
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/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
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/openbmc/linux/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
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/openbmc/linux/drivers/net/ethernet/intel/ixgbevf/
H A Ddefines.h8 #define IXGBE_DEV_ID_82599_VF 0x10ED
9 #define IXGBE_DEV_ID_X540_VF 0x1515
10 #define IXGBE_DEV_ID_X550_VF 0x1565
11 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
12 #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
14 #define IXGBE_DEV_ID_82599_VF_HV 0x152E
15 #define IXGBE_DEV_ID_X540_VF_HV 0x1530
16 #define IXGBE_DEV_ID_X550_VF_HV 0x1564
17 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
28 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
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/openbmc/linux/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
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/openbmc/linux/arch/mips/include/asm/sn/
H A Dioc3.h30 u8 iu_ier; /* DLAB == 0 */
34 u8 iu_rbr; /* read only, DLAB == 0 */
35 u8 iu_thr; /* write only, DLAB == 0 */
45 u8 fill[0x141]; /* starts at 0x141 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
69 struct ioc3_uartregs uartb; /* 0x20170 */
70 struct ioc3_uartregs uarta; /* 0x20178 */
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/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.h14 #define DDRSS_SS_ID_REV_REG 0x00000000
15 #define DDRSS_SS_CTL_REG 0x00000004
16 #define DDRSS_V2H_CTL_REG 0x00000020
18 #define SS_CTL_REG_CTL_ARST_SHIFT 0x0
22 #define DDRSS_DDRCTL_MSTR 0x00000000
23 #define DDRSS_DDRCTL_STAT 0x00000004
24 #define DDRSS_DDRCTL_MRCTRL0 0x00000010
25 #define DDRSS_DDRCTL_MRCTRL1 0x00000014
26 #define DDRSS_DDRCTL_MRSTAT 0x00000018
27 #define DDRSS_DDRCTL_MRCTRL2 0x0000001C
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/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h10 #define BCMA_CC_ID 0x0000
11 #define BCMA_CC_ID_ID 0x0000FFFF
12 #define BCMA_CC_ID_ID_SHIFT 0
13 #define BCMA_CC_ID_REV 0x000F0000
15 #define BCMA_CC_ID_PKG 0x00F00000
17 #define BCMA_CC_ID_NRCORES 0x0F000000
19 #define BCMA_CC_ID_TYPE 0xF0000000
21 #define BCMA_CC_CAP 0x0004 /* Capabilities */
22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
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/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_type.h12 #define IXGBE_DEV_ID_82598 0x10B6
13 #define IXGBE_DEV_ID_82598_BX 0x1508
14 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
15 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
16 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
17 #define IXGBE_DEV_ID_82598AT 0x10C8
18 #define IXGBE_DEV_ID_82598AT2 0x150B
19 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
20 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
21 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
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