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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-scc-qmc.yaml60 const: 0
63 '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
70 minimum: 0
125 reg = <0xa60 0x20>,
126 <0x3f00 0xc0>,
127 <0x2000 0x1000>;
133 #size-cells = <0>;
142 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
143 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
151 fsl,tx-ts-mask = <0x00000000 0x00000055>;
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs35l45-tables.c15 { 0x00000040, 0x00000055 },
16 { 0x00000040, 0x000000AA },
17 { 0x00000044, 0x00000055 },
18 { 0x00000044, 0x000000AA },
19 { 0x00006480, 0x0830500A },
20 { 0x00007C60, 0x1000850B },
21 { CS35L45_BOOST_OV_CFG, 0x007000D0 },
22 { CS35L45_LDPM_CONFIG, 0x0001B636 },
23 { 0x00002C08, 0x00000009 },
24 { 0x00006850, 0x0A30FFC4 },
[all …]
H A Dcs35l41-lib.c20 { CS35L41_PWR_CTRL1, 0x00000000 },
21 { CS35L41_PWR_CTRL2, 0x00000000 },
22 { CS35L41_PWR_CTRL3, 0x01000010 },
23 { CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
24 { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 },
25 { CS35L41_TST_FS_MON0, 0x00020016 },
26 { CS35L41_BSTCVRT_COEFF, 0x00002424 },
27 { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 },
28 { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A },
29 { CS35L41_SP_ENABLES, 0x00000000 },
[all …]
H A Dcs35l45.c50 unsigned int sts = 0, i; in cs35l45_set_cspl_mbox_cmd()
60 if (ret < 0) { in cs35l45_set_cspl_mbox_cmd()
67 for (i = 0; i < 5; i++) { in cs35l45_set_cspl_mbox_cmd()
71 if (ret < 0) { in cs35l45_set_cspl_mbox_cmd()
79 return 0; in cs35l45_set_cspl_mbox_cmd()
106 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, 0); in cs35l45_global_en_ev()
112 return 0; in cs35l45_global_en_ev()
125 return 0; in cs35l45_dsp_preload_ev()
130 return 0; in cs35l45_dsp_preload_ev()
138 return 0; in cs35l45_dsp_preload_ev()
[all …]
H A Dcs35l41.c39 { 32768, 0x00 },
40 { 8000, 0x01 },
41 { 11025, 0x02 },
42 { 12000, 0x03 },
43 { 16000, 0x04 },
44 { 22050, 0x05 },
45 { 24000, 0x06 },
46 { 32000, 0x07 },
47 { 44100, 0x08 },
48 { 48000, 0x09 },
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dinit.c86 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
88 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
92 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
94 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
98 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
101 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
104 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \ in mt76_write_mac_initvals()
107 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f)) in mt76_write_mac_initvals()
111 { MT_PBF_SYS_CTRL, 0x00080c00 }, in mt76_write_mac_initvals()
112 { MT_PBF_CFG, 0x1efebcff }, in mt76_write_mac_initvals()
[all …]
/openbmc/linux/drivers/staging/rts5208/
H A Dsd.h17 #define SUPPORT_VOLTAGE 0x003C0000
20 #define SD_NO_ERROR 0x0
21 #define SD_CRC_ERR 0x80
22 #define SD_TO_ERR 0x40
23 #define SD_NO_CARD 0x20
24 #define SD_BUSY 0x10
25 #define SD_STS_ERR 0x08
26 #define SD_RSP_TIMEOUT 0x04
27 #define SD_IO_ERR 0x02
30 #define SWITCH_SUCCESS 0
[all …]
/openbmc/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S29 * Swap <proto> (takes form 0xaabb)
31 * 0xbbaa0000 00000000
33 * 0xbbaa0000
37 * Assume input takes form 0xAABBCCDD
60 .frame $30,0,$26,0
62 .prologue 0
64 ldq_u $0,0($16) # L : Latency: 3
67 sll $19,8,$7 # U : U L U L : 0x00000000 00aabb00
72 ldq_u $2,0($17) # L : U L U L : Latency: 3
74 extql $0,$6,$0 # U :
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b_table.c10 0x029, 0x000000F9,
11 0x420, 0x00000080,
12 0x421, 0x0000001F,
13 0x428, 0x0000000A,
14 0x429, 0x00000010,
15 0x430, 0x00000000,
16 0x431, 0x00000000,
17 0x432, 0x00000000,
18 0x433, 0x00000001,
19 0x434, 0x00000004,
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9462_2p1_initvals.h63 {0x00000008, 0x00000000},
64 {0x00000030, 0x000e0085},
65 {0x00000034, 0x00000005},
66 {0x00000040, 0x00000000},
67 {0x00000044, 0x00000000},
68 {0x00000048, 0x00000008},
69 {0x0000004c, 0x00000010},
70 {0x00000050, 0x00000000},
71 {0x00001040, 0x002ffc0f},
72 {0x00001044, 0x002ffc0f},
[all …]
H A Dar5008_initvals.h19 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
20 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
21 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
22 {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000},
23 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
24 {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab},
25 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
26 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
27 {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300},
28 {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200},
[all …]
H A Dar955x_1p0_initvals.h33 {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
34 {0x0001609c, 0x0a566f3a, 0x0a566f3a, 0x0a566f3a, 0x0a566f3a},
35 {0x000160ac, 0xa4647c00, 0xa4647c00, 0x24647c00, 0x24647c00},
36 {0x000160b0, 0x01885f52, 0x01885f52, 0x01885f52, 0x01885f52},
37 {0x00016104, 0xb7a00000, 0xb7a00000, 0xb7a00001, 0xb7a00001},
38 {0x0001610c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
39 {0x00016140, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
40 {0x00016504, 0xb7a00000, 0xb7a00000, 0xb7a00001, 0xb7a00001},
41 {0x0001650c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
42 {0x00016540, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
[all …]
H A Dar9565_1p0_initvals.h31 {0x00000008, 0x00000000},
32 {0x00000030, 0x000a0085},
33 {0x00000034, 0x00000005},
34 {0x00000040, 0x00000000},
35 {0x00000044, 0x00000000},
36 {0x00000048, 0x00000008},
37 {0x0000004c, 0x00000010},
38 {0x00000050, 0x00000000},
39 {0x00001040, 0x002ffc0f},
40 {0x00001044, 0x002ffc0f},
[all …]
H A Dar9330_1p1_initvals.h27 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
28 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
29 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
30 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
31 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
32 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
33 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
34 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
35 {0x00009e04, 0x00202020, 0x00202020, 0x00202020, 0x00202020},
36 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
[all …]
H A Dar9462_2p0_initvals.h33 {0x00001030, 0x00000268, 0x000004d0},
34 {0x00001070, 0x0000018c, 0x00000318},
35 {0x000010b0, 0x00000fd0, 0x00001fa0},
36 {0x00008014, 0x044c044c, 0x08980898},
37 {0x0000801c, 0x148ec02b, 0x148ec057},
38 {0x00008318, 0x000044c0, 0x00008980},
39 {0x00009e00, 0x0372131c, 0x0372131c},
40 {0x0000a230, 0x0000400b, 0x00004016},
41 {0x0000a254, 0x00000898, 0x00001130},
46 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Dinitvals.c32 * @ini_mode: 0 to write 1 to read (and clear)
39 AR5K_INI_WRITE = 0, /* Default */
57 { AR5K_NOQCU_TXDP0, 0 },
58 { AR5K_NOQCU_TXDP1, 0 },
59 { AR5K_RXDP, 0 },
60 { AR5K_CR, 0 },
61 { AR5K_ISR, 0, AR5K_INI_READ },
62 { AR5K_IMR, 0 },
64 { AR5K_BSR, 0, AR5K_INI_READ },
70 { AR5K_RPGTO, 0 },
[all …]
H A Drfgain.h38 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
39 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
40 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
41 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
42 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
43 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
44 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
45 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
46 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
47 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
[all …]
/openbmc/linux/drivers/net/wireless/ath/carl9170/
H A Dphy.c48 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f); in carl9170_init_power_cal()
49 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f); in carl9170_init_power_cal()
50 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f); in carl9170_init_power_cal()
51 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f); in carl9170_init_power_cal()
52 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f); in carl9170_init_power_cal()
53 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f); in carl9170_init_power_cal()
54 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f); in carl9170_init_power_cal()
55 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f); in carl9170_init_power_cal()
56 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f); in carl9170_init_power_cal()
57 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f); in carl9170_init_power_cal()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
H A Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
H A Dsoc21_enum.h55 DSM_DATA_SEL_DISABLE = 0x00000000,
56 DSM_DATA_SEL_0 = 0x00000001,
57 DSM_DATA_SEL_1 = 0x00000002,
58 DSM_DATA_SEL_BOTH = 0x00000003,
66 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
67 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
68 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
69 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
77 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
78 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
[all …]
/openbmc/linux/drivers/scsi/
H A D53c700_d.h_shipped28 ABSOLUTE Device_ID = 0 ; ID of target for command
29 ABSOLUTE MessageCount = 0 ; Number of bytes in message
30 ABSOLUTE MessageLocation = 0 ; Addr of message
31 ABSOLUTE CommandCount = 0 ; Number of bytes in command
32 ABSOLUTE CommandAddress = 0 ; Addr of Command
33 ABSOLUTE StatusAddress = 0 ; Addr to receive status return
34 ABSOLUTE ReceiveMsgAddress = 0 ; Addr to receive msg
42 ABSOLUTE SGScriptStartAddress = 0
45 ; this: 0xPRS where
48 ABSOLUTE AFTER_SELECTION = 0x100
[all …]
/openbmc/linux/drivers/mfd/
H A Dcs42l43.c36 #define CS42L43_MCU_UPDATE_OFFSET 0x100000
40 #define CS42L43_MCU_SUPPORTED_REV 0x2105
41 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200
42 #define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001
66 { 0x4000, 0x00000055 },
67 { 0x4000, 0x000000AA },
68 { 0x10084, 0x00000000 },
69 { 0x1741C, 0x00CD2000 },
70 { 0x1718C, 0x00000003 },
71 { 0x4000, 0x00000000 },
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/u-boot/include/
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]

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