1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // cs35l41.c -- CS35l41 ALSA SoC audio driver
4 //
5 // Copyright 2017-2021 Cirrus Logic, Inc.
6 //
7 // Author: David Rhodes <david.rhodes@cirrus.com>
8
9 #include <linux/acpi.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/of_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/property.h>
19 #include <sound/initval.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/tlv.h>
25
26 #include "cs35l41.h"
27
28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = {
29 "VA",
30 "VP",
31 };
32
33 struct cs35l41_pll_sysclk_config {
34 int freq;
35 int clk_cfg;
36 };
37
38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = {
39 { 32768, 0x00 },
40 { 8000, 0x01 },
41 { 11025, 0x02 },
42 { 12000, 0x03 },
43 { 16000, 0x04 },
44 { 22050, 0x05 },
45 { 24000, 0x06 },
46 { 32000, 0x07 },
47 { 44100, 0x08 },
48 { 48000, 0x09 },
49 { 88200, 0x0A },
50 { 96000, 0x0B },
51 { 128000, 0x0C },
52 { 176400, 0x0D },
53 { 192000, 0x0E },
54 { 256000, 0x0F },
55 { 352800, 0x10 },
56 { 384000, 0x11 },
57 { 512000, 0x12 },
58 { 705600, 0x13 },
59 { 750000, 0x14 },
60 { 768000, 0x15 },
61 { 1000000, 0x16 },
62 { 1024000, 0x17 },
63 { 1200000, 0x18 },
64 { 1411200, 0x19 },
65 { 1500000, 0x1A },
66 { 1536000, 0x1B },
67 { 2000000, 0x1C },
68 { 2048000, 0x1D },
69 { 2400000, 0x1E },
70 { 2822400, 0x1F },
71 { 3000000, 0x20 },
72 { 3072000, 0x21 },
73 { 3200000, 0x22 },
74 { 4000000, 0x23 },
75 { 4096000, 0x24 },
76 { 4800000, 0x25 },
77 { 5644800, 0x26 },
78 { 6000000, 0x27 },
79 { 6144000, 0x28 },
80 { 6250000, 0x29 },
81 { 6400000, 0x2A },
82 { 6500000, 0x2B },
83 { 6750000, 0x2C },
84 { 7526400, 0x2D },
85 { 8000000, 0x2E },
86 { 8192000, 0x2F },
87 { 9600000, 0x30 },
88 { 11289600, 0x31 },
89 { 12000000, 0x32 },
90 { 12288000, 0x33 },
91 { 12500000, 0x34 },
92 { 12800000, 0x35 },
93 { 13000000, 0x36 },
94 { 13500000, 0x37 },
95 { 19200000, 0x38 },
96 { 22579200, 0x39 },
97 { 24000000, 0x3A },
98 { 24576000, 0x3B },
99 { 25000000, 0x3C },
100 { 25600000, 0x3D },
101 { 26000000, 0x3E },
102 { 27000000, 0x3F },
103 };
104
105 struct cs35l41_fs_mon_config {
106 int freq;
107 unsigned int fs1;
108 unsigned int fs2;
109 };
110
111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = {
112 { 32768, 2254, 3754 },
113 { 8000, 9220, 15364 },
114 { 11025, 6148, 10244 },
115 { 12000, 6148, 10244 },
116 { 16000, 4612, 7684 },
117 { 22050, 3076, 5124 },
118 { 24000, 3076, 5124 },
119 { 32000, 2308, 3844 },
120 { 44100, 1540, 2564 },
121 { 48000, 1540, 2564 },
122 { 88200, 772, 1284 },
123 { 96000, 772, 1284 },
124 { 128000, 580, 964 },
125 { 176400, 388, 644 },
126 { 192000, 388, 644 },
127 { 256000, 292, 484 },
128 { 352800, 196, 324 },
129 { 384000, 196, 324 },
130 { 512000, 148, 244 },
131 { 705600, 100, 164 },
132 { 750000, 100, 164 },
133 { 768000, 100, 164 },
134 { 1000000, 76, 124 },
135 { 1024000, 76, 124 },
136 { 1200000, 64, 104 },
137 { 1411200, 52, 84 },
138 { 1500000, 52, 84 },
139 { 1536000, 52, 84 },
140 { 2000000, 40, 64 },
141 { 2048000, 40, 64 },
142 { 2400000, 34, 54 },
143 { 2822400, 28, 44 },
144 { 3000000, 28, 44 },
145 { 3072000, 28, 44 },
146 { 3200000, 27, 42 },
147 { 4000000, 22, 34 },
148 { 4096000, 22, 34 },
149 { 4800000, 19, 29 },
150 { 5644800, 16, 24 },
151 { 6000000, 16, 24 },
152 { 6144000, 16, 24 },
153 { 12288000, 0, 0 },
154 };
155
cs35l41_get_fs_mon_config_index(int freq)156 static int cs35l41_get_fs_mon_config_index(int freq)
157 {
158 int i;
159
160 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) {
161 if (cs35l41_fs_mon[i].freq == freq)
162 return i;
163 }
164
165 return -EINVAL;
166 }
167
168 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv,
169 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
170 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200));
171 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 50, 100, 0);
172
173 static const struct snd_kcontrol_new dre_ctrl =
174 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0);
175
176 static const char * const cs35l41_pcm_sftramp_text[] = {
177 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"
178 };
179
180 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp,
181 CS35L41_AMP_DIG_VOL_CTRL, 0,
182 cs35l41_pcm_sftramp_text);
183
cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)184 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w,
185 struct snd_kcontrol *kcontrol, int event)
186 {
187 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
188 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
189 int ret;
190
191 switch (event) {
192 case SND_SOC_DAPM_PRE_PMU:
193 if (cs35l41->dsp.cs_dsp.booted)
194 return 0;
195
196 return wm_adsp_early_event(w, kcontrol, event);
197 case SND_SOC_DAPM_PRE_PMD:
198 if (cs35l41->dsp.preloaded)
199 return 0;
200
201 if (cs35l41->dsp.cs_dsp.running) {
202 ret = wm_adsp_event(w, kcontrol, event);
203 if (ret)
204 return ret;
205 }
206
207 return wm_adsp_early_event(w, kcontrol, event);
208 default:
209 return 0;
210 }
211 }
212
cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)213 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w,
214 struct snd_kcontrol *kcontrol, int event)
215 {
216 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
217 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
218 unsigned int fw_status;
219 int ret;
220
221 switch (event) {
222 case SND_SOC_DAPM_POST_PMU:
223 if (!cs35l41->dsp.cs_dsp.running)
224 return wm_adsp_event(w, kcontrol, event);
225
226 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status);
227 if (ret < 0) {
228 dev_err(cs35l41->dev,
229 "Failed to read firmware status: %d\n", ret);
230 return ret;
231 }
232
233 switch (fw_status) {
234 case CSPL_MBOX_STS_RUNNING:
235 case CSPL_MBOX_STS_PAUSED:
236 break;
237 default:
238 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n",
239 fw_status);
240 return -EINVAL;
241 }
242
243 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
244 CSPL_MBOX_CMD_RESUME);
245 case SND_SOC_DAPM_PRE_PMD:
246 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
247 CSPL_MBOX_CMD_PAUSE);
248 default:
249 return 0;
250 }
251 }
252
253 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"};
254 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32};
255 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum,
256 CS35L41_DAC_PCM1_SRC,
257 0, CS35L41_ASP_SOURCE_MASK,
258 cs35l41_pcm_source_texts,
259 cs35l41_pcm_source_values);
260
261 static const struct snd_kcontrol_new pcm_source_mux =
262 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum);
263
264 static const char * const cs35l41_tx_input_texts[] = {
265 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON",
266 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2"
267 };
268
269 static const unsigned int cs35l41_tx_input_values[] = {
270 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2,
271 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON,
272 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2
273 };
274
275 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum,
276 CS35L41_ASP_TX1_SRC,
277 0, CS35L41_ASP_SOURCE_MASK,
278 cs35l41_tx_input_texts,
279 cs35l41_tx_input_values);
280
281 static const struct snd_kcontrol_new asp_tx1_mux =
282 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum);
283
284 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum,
285 CS35L41_ASP_TX2_SRC,
286 0, CS35L41_ASP_SOURCE_MASK,
287 cs35l41_tx_input_texts,
288 cs35l41_tx_input_values);
289
290 static const struct snd_kcontrol_new asp_tx2_mux =
291 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum);
292
293 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum,
294 CS35L41_ASP_TX3_SRC,
295 0, CS35L41_ASP_SOURCE_MASK,
296 cs35l41_tx_input_texts,
297 cs35l41_tx_input_values);
298
299 static const struct snd_kcontrol_new asp_tx3_mux =
300 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum);
301
302 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum,
303 CS35L41_ASP_TX4_SRC,
304 0, CS35L41_ASP_SOURCE_MASK,
305 cs35l41_tx_input_texts,
306 cs35l41_tx_input_values);
307
308 static const struct snd_kcontrol_new asp_tx4_mux =
309 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum);
310
311 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum,
312 CS35L41_DSP1_RX1_SRC,
313 0, CS35L41_ASP_SOURCE_MASK,
314 cs35l41_tx_input_texts,
315 cs35l41_tx_input_values);
316
317 static const struct snd_kcontrol_new dsp_rx1_mux =
318 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum);
319
320 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum,
321 CS35L41_DSP1_RX2_SRC,
322 0, CS35L41_ASP_SOURCE_MASK,
323 cs35l41_tx_input_texts,
324 cs35l41_tx_input_values);
325
326 static const struct snd_kcontrol_new dsp_rx2_mux =
327 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum);
328
329 static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
330 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL,
331 3, 0x4CF, 0x391, dig_vol_tlv),
332 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0,
333 amp_gain_tlv),
334 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
335 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0),
336 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0),
337 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0),
338 SOC_SINGLE("Aux Noise Gate CH1 Switch",
339 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0),
340 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay",
341 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0),
342 SOC_SINGLE("Aux Noise Gate CH1 Threshold",
343 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0),
344 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay",
345 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0),
346 SOC_SINGLE("Aux Noise Gate CH2 Switch",
347 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0),
348 SOC_SINGLE("Aux Noise Gate CH2 Threshold",
349 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0),
350 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
351 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
352 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL,
353 CS35L41_AMP_INV_PCM_SHIFT, 1, 0),
354 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL,
355 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0),
356 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
357 WM_ADSP_FW_CONTROL("DSP1", 0),
358 };
359
cs35l41_boost_enable(struct cs35l41_private * cs35l41,unsigned int enable)360 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable)
361 {
362 switch (cs35l41->hw_cfg.bst_type) {
363 case CS35L41_INT_BOOST:
364 case CS35L41_SHD_BOOST_ACTV:
365 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF;
366 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
367 enable << CS35L41_BST_EN_SHIFT);
368 break;
369 default:
370 break;
371 }
372 }
373
374
cs35l41_error_release(struct cs35l41_private * cs35l41,unsigned int irq_err_bit,unsigned int rel_err_bit)375 static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit,
376 unsigned int rel_err_bit)
377 {
378 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit);
379 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
380 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit);
381 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0);
382 }
383
cs35l41_irq(int irq,void * data)384 static irqreturn_t cs35l41_irq(int irq, void *data)
385 {
386 struct cs35l41_private *cs35l41 = data;
387 unsigned int status[4] = { 0, 0, 0, 0 };
388 unsigned int masks[4] = { 0, 0, 0, 0 };
389 unsigned int i;
390 int ret;
391
392 ret = pm_runtime_resume_and_get(cs35l41->dev);
393 if (ret < 0) {
394 dev_err(cs35l41->dev,
395 "pm_runtime_resume_and_get failed in %s: %d\n",
396 __func__, ret);
397 return IRQ_NONE;
398 }
399
400 ret = IRQ_NONE;
401
402 for (i = 0; i < ARRAY_SIZE(status); i++) {
403 regmap_read(cs35l41->regmap,
404 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE),
405 &status[i]);
406 regmap_read(cs35l41->regmap,
407 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE),
408 &masks[i]);
409 }
410
411 /* Check to see if unmasked bits are active */
412 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
413 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3]))
414 goto done;
415
416 if (status[3] & CS35L41_OTP_BOOT_DONE) {
417 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4,
418 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE);
419 }
420
421 /*
422 * The following interrupts require a
423 * protection release cycle to get the
424 * speaker out of Safe-Mode.
425 */
426 if (status[0] & CS35L41_AMP_SHORT_ERR) {
427 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n");
428 cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS);
429 ret = IRQ_HANDLED;
430 }
431
432 if (status[0] & CS35L41_TEMP_WARN) {
433 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n");
434 cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS);
435 ret = IRQ_HANDLED;
436 }
437
438 if (status[0] & CS35L41_TEMP_ERR) {
439 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n");
440 cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS);
441 ret = IRQ_HANDLED;
442 }
443
444 if (status[0] & CS35L41_BST_OVP_ERR) {
445 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n");
446 cs35l41_boost_enable(cs35l41, 0);
447 cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS);
448 cs35l41_boost_enable(cs35l41, 1);
449 ret = IRQ_HANDLED;
450 }
451
452 if (status[0] & CS35L41_BST_DCM_UVP_ERR) {
453 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n");
454 cs35l41_boost_enable(cs35l41, 0);
455 cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS);
456 cs35l41_boost_enable(cs35l41, 1);
457 ret = IRQ_HANDLED;
458 }
459
460 if (status[0] & CS35L41_BST_SHORT_ERR) {
461 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n");
462 cs35l41_boost_enable(cs35l41, 0);
463 cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS);
464 cs35l41_boost_enable(cs35l41, 1);
465 ret = IRQ_HANDLED;
466 }
467
468 if (status[2] & CS35L41_PLL_LOCK) {
469 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS3, CS35L41_PLL_LOCK);
470
471 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV ||
472 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS) {
473 ret = cs35l41_mdsync_up(cs35l41->regmap);
474 if (ret)
475 dev_err(cs35l41->dev, "MDSYNC-up failed: %d\n", ret);
476 else
477 dev_dbg(cs35l41->dev, "MDSYNC-up done\n");
478
479 dev_dbg(cs35l41->dev, "PUP-done status: %d\n",
480 !!(status[0] & CS35L41_PUP_DONE_MASK));
481 }
482
483 ret = IRQ_HANDLED;
484 }
485
486 done:
487 pm_runtime_mark_last_busy(cs35l41->dev);
488 pm_runtime_put_autosuspend(cs35l41->dev);
489
490 return ret;
491 }
492
493 static const struct reg_sequence cs35l41_pup_patch[] = {
494 { CS35L41_TEST_KEY_CTL, 0x00000055 },
495 { CS35L41_TEST_KEY_CTL, 0x000000AA },
496 { 0x00002084, 0x002F1AA0 },
497 { CS35L41_TEST_KEY_CTL, 0x000000CC },
498 { CS35L41_TEST_KEY_CTL, 0x00000033 },
499 };
500
501 static const struct reg_sequence cs35l41_pdn_patch[] = {
502 { CS35L41_TEST_KEY_CTL, 0x00000055 },
503 { CS35L41_TEST_KEY_CTL, 0x000000AA },
504 { 0x00002084, 0x002F1AA3 },
505 { CS35L41_TEST_KEY_CTL, 0x000000CC },
506 { CS35L41_TEST_KEY_CTL, 0x00000033 },
507 };
508
cs35l41_main_amp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)509 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
510 struct snd_kcontrol *kcontrol, int event)
511 {
512 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
513 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
514 int ret = 0;
515
516 switch (event) {
517 case SND_SOC_DAPM_PRE_PMU:
518 regmap_multi_reg_write_bypassed(cs35l41->regmap,
519 cs35l41_pup_patch,
520 ARRAY_SIZE(cs35l41_pup_patch));
521
522 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
523 1, cs35l41->dsp.cs_dsp.running);
524 break;
525 case SND_SOC_DAPM_POST_PMD:
526 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
527 0, cs35l41->dsp.cs_dsp.running);
528
529 regmap_multi_reg_write_bypassed(cs35l41->regmap,
530 cs35l41_pdn_patch,
531 ARRAY_SIZE(cs35l41_pdn_patch));
532 break;
533 default:
534 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event);
535 ret = -EINVAL;
536 }
537
538 return ret;
539 }
540
541 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = {
542 SND_SOC_DAPM_SPK("DSP1 Preload", NULL),
543 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0,
544 cs35l41_dsp_preload_ev,
545 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
546 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0,
547 cs35l41_dsp_audio_ev,
548 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
549
550 SND_SOC_DAPM_OUTPUT("SPK"),
551
552 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0),
553 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0),
554 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0),
555 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0),
556 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0),
557 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0),
558
559 SND_SOC_DAPM_SIGGEN("VSENSE"),
560 SND_SOC_DAPM_SIGGEN("ISENSE"),
561 SND_SOC_DAPM_SIGGEN("VP"),
562 SND_SOC_DAPM_SIGGEN("VBST"),
563 SND_SOC_DAPM_SIGGEN("TEMP"),
564
565 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0),
566 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0),
567 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0),
568 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0),
569 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0),
570
571 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0),
572 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0),
573 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
574 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0),
575 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
576
577 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0),
578
579 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0,
580 cs35l41_main_amp_event,
581 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
582
583 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux),
584 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux),
585 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux),
586 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux),
587 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux),
588 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux),
589 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux),
590 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl),
591 };
592
593 static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
594 {"DSP RX1 Source", "ASPRX1", "ASPRX1"},
595 {"DSP RX1 Source", "ASPRX2", "ASPRX2"},
596 {"DSP RX2 Source", "ASPRX1", "ASPRX1"},
597 {"DSP RX2 Source", "ASPRX2", "ASPRX2"},
598
599 {"DSP1", NULL, "DSP RX1 Source"},
600 {"DSP1", NULL, "DSP RX2 Source"},
601
602 {"ASP TX1 Source", "VMON", "VMON ADC"},
603 {"ASP TX1 Source", "IMON", "IMON ADC"},
604 {"ASP TX1 Source", "VPMON", "VPMON ADC"},
605 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"},
606 {"ASP TX1 Source", "DSPTX1", "DSP1"},
607 {"ASP TX1 Source", "DSPTX2", "DSP1"},
608 {"ASP TX1 Source", "ASPRX1", "ASPRX1" },
609 {"ASP TX1 Source", "ASPRX2", "ASPRX2" },
610 {"ASP TX2 Source", "VMON", "VMON ADC"},
611 {"ASP TX2 Source", "IMON", "IMON ADC"},
612 {"ASP TX2 Source", "VPMON", "VPMON ADC"},
613 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"},
614 {"ASP TX2 Source", "DSPTX1", "DSP1"},
615 {"ASP TX2 Source", "DSPTX2", "DSP1"},
616 {"ASP TX2 Source", "ASPRX1", "ASPRX1" },
617 {"ASP TX2 Source", "ASPRX2", "ASPRX2" },
618 {"ASP TX3 Source", "VMON", "VMON ADC"},
619 {"ASP TX3 Source", "IMON", "IMON ADC"},
620 {"ASP TX3 Source", "VPMON", "VPMON ADC"},
621 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"},
622 {"ASP TX3 Source", "DSPTX1", "DSP1"},
623 {"ASP TX3 Source", "DSPTX2", "DSP1"},
624 {"ASP TX3 Source", "ASPRX1", "ASPRX1" },
625 {"ASP TX3 Source", "ASPRX2", "ASPRX2" },
626 {"ASP TX4 Source", "VMON", "VMON ADC"},
627 {"ASP TX4 Source", "IMON", "IMON ADC"},
628 {"ASP TX4 Source", "VPMON", "VPMON ADC"},
629 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"},
630 {"ASP TX4 Source", "DSPTX1", "DSP1"},
631 {"ASP TX4 Source", "DSPTX2", "DSP1"},
632 {"ASP TX4 Source", "ASPRX1", "ASPRX1" },
633 {"ASP TX4 Source", "ASPRX2", "ASPRX2" },
634 {"ASPTX1", NULL, "ASP TX1 Source"},
635 {"ASPTX2", NULL, "ASP TX2 Source"},
636 {"ASPTX3", NULL, "ASP TX3 Source"},
637 {"ASPTX4", NULL, "ASP TX4 Source"},
638 {"AMP Capture", NULL, "ASPTX1"},
639 {"AMP Capture", NULL, "ASPTX2"},
640 {"AMP Capture", NULL, "ASPTX3"},
641 {"AMP Capture", NULL, "ASPTX4"},
642
643 {"DSP1", NULL, "VMON"},
644 {"DSP1", NULL, "IMON"},
645 {"DSP1", NULL, "VPMON"},
646 {"DSP1", NULL, "VBSTMON"},
647 {"DSP1", NULL, "TEMPMON"},
648
649 {"VMON ADC", NULL, "VMON"},
650 {"IMON ADC", NULL, "IMON"},
651 {"VPMON ADC", NULL, "VPMON"},
652 {"VBSTMON ADC", NULL, "VBSTMON"},
653 {"TEMPMON ADC", NULL, "TEMPMON"},
654
655 {"VMON ADC", NULL, "VSENSE"},
656 {"IMON ADC", NULL, "ISENSE"},
657 {"VPMON ADC", NULL, "VP"},
658 {"VBSTMON ADC", NULL, "VBST"},
659 {"TEMPMON ADC", NULL, "TEMP"},
660
661 {"DSP1 Preload", NULL, "DSP1 Preloader"},
662 {"DSP1", NULL, "DSP1 Preloader"},
663
664 {"ASPRX1", NULL, "AMP Playback"},
665 {"ASPRX2", NULL, "AMP Playback"},
666 {"DRE", "Switch", "CLASS H"},
667 {"Main AMP", NULL, "CLASS H"},
668 {"Main AMP", NULL, "DRE"},
669 {"SPK", NULL, "Main AMP"},
670
671 {"PCM Source", "ASP", "ASPRX1"},
672 {"PCM Source", "DSP", "DSP1"},
673 {"CLASS H", NULL, "PCM Source"},
674 };
675
cs35l41_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_n,unsigned int * tx_slot,unsigned int rx_n,unsigned int * rx_slot)676 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n,
677 unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot)
678 {
679 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
680
681 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot);
682 }
683
cs35l41_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)684 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
685 {
686 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
687 unsigned int daifmt = 0;
688
689 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
690 case SND_SOC_DAIFMT_CBP_CFP:
691 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK;
692 break;
693 case SND_SOC_DAIFMT_CBC_CFC:
694 break;
695 default:
696 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n");
697 return -EINVAL;
698 }
699
700 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
701 case SND_SOC_DAIFMT_DSP_A:
702 break;
703 case SND_SOC_DAIFMT_I2S:
704 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT;
705 break;
706 default:
707 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n");
708 return -EINVAL;
709 }
710
711 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
712 case SND_SOC_DAIFMT_NB_IF:
713 daifmt |= CS35L41_LRCLK_INV_MASK;
714 break;
715 case SND_SOC_DAIFMT_IB_NF:
716 daifmt |= CS35L41_SCLK_INV_MASK;
717 break;
718 case SND_SOC_DAIFMT_IB_IF:
719 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK;
720 break;
721 case SND_SOC_DAIFMT_NB_NF:
722 break;
723 default:
724 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n");
725 return -EINVAL;
726 }
727
728 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
729 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK |
730 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK |
731 CS35L41_SCLK_INV_MASK, daifmt);
732 }
733
734 struct cs35l41_global_fs_config {
735 int rate;
736 int fs_cfg;
737 };
738
739 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = {
740 { 12000, 0x01 },
741 { 24000, 0x02 },
742 { 48000, 0x03 },
743 { 96000, 0x04 },
744 { 192000, 0x05 },
745 { 11025, 0x09 },
746 { 22050, 0x0A },
747 { 44100, 0x0B },
748 { 88200, 0x0C },
749 { 176400, 0x0D },
750 { 8000, 0x11 },
751 { 16000, 0x12 },
752 { 32000, 0x13 },
753 };
754
cs35l41_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)755 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream,
756 struct snd_pcm_hw_params *params,
757 struct snd_soc_dai *dai)
758 {
759 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
760 unsigned int rate = params_rate(params);
761 u8 asp_wl;
762 int i;
763
764 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) {
765 if (rate == cs35l41_fs_rates[i].rate)
766 break;
767 }
768
769 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) {
770 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate);
771 return -EINVAL;
772 }
773
774 asp_wl = params_width(params);
775
776 if (i < ARRAY_SIZE(cs35l41_fs_rates))
777 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL,
778 CS35L41_GLOBAL_FS_MASK,
779 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT);
780
781 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
782 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
783 CS35L41_ASP_WIDTH_RX_MASK,
784 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT);
785 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL,
786 CS35L41_ASP_RX_WL_MASK,
787 asp_wl << CS35L41_ASP_RX_WL_SHIFT);
788 } else {
789 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
790 CS35L41_ASP_WIDTH_TX_MASK,
791 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT);
792 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL,
793 CS35L41_ASP_TX_WL_MASK,
794 asp_wl << CS35L41_ASP_TX_WL_SHIFT);
795 }
796
797 return 0;
798 }
799
cs35l41_get_clk_config(int freq)800 static int cs35l41_get_clk_config(int freq)
801 {
802 int i;
803
804 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) {
805 if (cs35l41_pll_sysclk[i].freq == freq)
806 return cs35l41_pll_sysclk[i].clk_cfg;
807 }
808
809 return -EINVAL;
810 }
811
812 static const unsigned int cs35l41_src_rates[] = {
813 8000, 12000, 11025, 16000, 22050, 24000, 32000,
814 44100, 48000, 88200, 96000, 176400, 192000
815 };
816
817 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = {
818 .count = ARRAY_SIZE(cs35l41_src_rates),
819 .list = cs35l41_src_rates,
820 };
821
cs35l41_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)822 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream,
823 struct snd_soc_dai *dai)
824 {
825 if (substream->runtime)
826 return snd_pcm_hw_constraint_list(substream->runtime, 0,
827 SNDRV_PCM_HW_PARAM_RATE,
828 &cs35l41_constraints);
829 return 0;
830 }
831
cs35l41_component_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)832 static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
833 int clk_id, int source,
834 unsigned int freq, int dir)
835 {
836 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
837 int extclk_cfg, clksrc;
838
839 switch (clk_id) {
840 case CS35L41_CLKID_SCLK:
841 clksrc = CS35L41_PLLSRC_SCLK;
842 break;
843 case CS35L41_CLKID_LRCLK:
844 clksrc = CS35L41_PLLSRC_LRCLK;
845 break;
846 case CS35L41_CLKID_MCLK:
847 clksrc = CS35L41_PLLSRC_MCLK;
848 break;
849 default:
850 dev_err(cs35l41->dev, "Invalid CLK Config\n");
851 return -EINVAL;
852 }
853
854 extclk_cfg = cs35l41_get_clk_config(freq);
855
856 if (extclk_cfg < 0) {
857 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n",
858 extclk_cfg, freq);
859 return -EINVAL;
860 }
861
862 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
863 CS35L41_PLL_OPENLOOP_MASK,
864 1 << CS35L41_PLL_OPENLOOP_SHIFT);
865 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
866 CS35L41_REFCLK_FREQ_MASK,
867 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT);
868 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
869 CS35L41_PLL_CLK_EN_MASK,
870 0 << CS35L41_PLL_CLK_EN_SHIFT);
871 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
872 CS35L41_PLL_CLK_SEL_MASK, clksrc);
873 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
874 CS35L41_PLL_OPENLOOP_MASK,
875 0 << CS35L41_PLL_OPENLOOP_SHIFT);
876 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
877 CS35L41_PLL_CLK_EN_MASK,
878 1 << CS35L41_PLL_CLK_EN_SHIFT);
879
880 return 0;
881 }
882
cs35l41_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)883 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai,
884 int clk_id, unsigned int freq, int dir)
885 {
886 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
887 unsigned int fs1_val;
888 unsigned int fs2_val;
889 unsigned int val;
890 int fsindex;
891
892 fsindex = cs35l41_get_fs_mon_config_index(freq);
893 if (fsindex < 0) {
894 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq);
895 return -EINVAL;
896 }
897
898 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq);
899
900 if (freq <= 6144000) {
901 /* Use the lookup table */
902 fs1_val = cs35l41_fs_mon[fsindex].fs1;
903 fs2_val = cs35l41_fs_mon[fsindex].fs2;
904 } else {
905 /* Use hard-coded values */
906 fs1_val = 0x10;
907 fs2_val = 0x24;
908 }
909
910 val = fs1_val;
911 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK;
912 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val);
913
914 return 0;
915 }
916
cs35l41_set_pdata(struct cs35l41_private * cs35l41)917 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41)
918 {
919 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
920 int ret;
921
922 if (!hw_cfg->valid)
923 return -EINVAL;
924
925 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH)
926 return -EINVAL;
927
928 /* Required */
929 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg);
930 if (ret)
931 return ret;
932
933 /* Optional */
934 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0)
935 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK,
936 hw_cfg->dout_hiz);
937
938 return 0;
939 }
940
941 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = {
942 {"Main AMP", NULL, "VSPK"},
943 };
944
945 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = {
946 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0),
947 };
948
cs35l41_component_probe(struct snd_soc_component * component)949 static int cs35l41_component_probe(struct snd_soc_component *component)
950 {
951 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
952 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
953 int ret;
954
955 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) {
956 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget,
957 ARRAY_SIZE(cs35l41_ext_bst_widget));
958 if (ret)
959 return ret;
960
961 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes,
962 ARRAY_SIZE(cs35l41_ext_bst_routes));
963 if (ret)
964 return ret;
965 }
966
967 return wm_adsp2_component_probe(&cs35l41->dsp, component);
968 }
969
cs35l41_component_remove(struct snd_soc_component * component)970 static void cs35l41_component_remove(struct snd_soc_component *component)
971 {
972 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
973
974 wm_adsp2_component_remove(&cs35l41->dsp, component);
975 }
976
977 static const struct snd_soc_dai_ops cs35l41_ops = {
978 .startup = cs35l41_pcm_startup,
979 .set_fmt = cs35l41_set_dai_fmt,
980 .hw_params = cs35l41_pcm_hw_params,
981 .set_sysclk = cs35l41_dai_set_sysclk,
982 .set_channel_map = cs35l41_set_channel_map,
983 };
984
985 static struct snd_soc_dai_driver cs35l41_dai[] = {
986 {
987 .name = "cs35l41-pcm",
988 .id = 0,
989 .playback = {
990 .stream_name = "AMP Playback",
991 .channels_min = 1,
992 .channels_max = 2,
993 .rates = SNDRV_PCM_RATE_KNOT,
994 .formats = CS35L41_RX_FORMATS,
995 },
996 .capture = {
997 .stream_name = "AMP Capture",
998 .channels_min = 1,
999 .channels_max = 4,
1000 .rates = SNDRV_PCM_RATE_KNOT,
1001 .formats = CS35L41_TX_FORMATS,
1002 },
1003 .ops = &cs35l41_ops,
1004 .symmetric_rate = 1,
1005 },
1006 };
1007
1008 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = {
1009 .name = "cs35l41-codec",
1010 .probe = cs35l41_component_probe,
1011 .remove = cs35l41_component_remove,
1012
1013 .dapm_widgets = cs35l41_dapm_widgets,
1014 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets),
1015 .dapm_routes = cs35l41_audio_map,
1016 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map),
1017
1018 .controls = cs35l41_aud_controls,
1019 .num_controls = ARRAY_SIZE(cs35l41_aud_controls),
1020 .set_sysclk = cs35l41_component_set_sysclk,
1021
1022 .endianness = 1,
1023 };
1024
cs35l41_handle_pdata(struct device * dev,struct cs35l41_hw_cfg * hw_cfg)1025 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg)
1026 {
1027 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1;
1028 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2;
1029 unsigned int val;
1030 int ret;
1031
1032 /* Some ACPI systems received the Shared Boost feature before the upstream driver,
1033 * leaving those systems with deprecated _DSD properties.
1034 * To correctly configure those systems add shared-boost-active and shared-boost-passive
1035 * properties mapped to the correct value in boost-type.
1036 * These two are not DT properties and should not be used in new systems designs.
1037 */
1038 if (device_property_read_bool(dev, "cirrus,shared-boost-active")) {
1039 hw_cfg->bst_type = CS35L41_SHD_BOOST_ACTV;
1040 } else if (device_property_read_bool(dev, "cirrus,shared-boost-passive")) {
1041 hw_cfg->bst_type = CS35L41_SHD_BOOST_PASS;
1042 } else {
1043 ret = device_property_read_u32(dev, "cirrus,boost-type", &val);
1044 if (ret >= 0)
1045 hw_cfg->bst_type = val;
1046 }
1047
1048 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val);
1049 if (ret >= 0)
1050 hw_cfg->bst_ipk = val;
1051 else
1052 hw_cfg->bst_ipk = -1;
1053
1054 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val);
1055 if (ret >= 0)
1056 hw_cfg->bst_ind = val;
1057 else
1058 hw_cfg->bst_ind = -1;
1059
1060 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val);
1061 if (ret >= 0)
1062 hw_cfg->bst_cap = val;
1063 else
1064 hw_cfg->bst_cap = -1;
1065
1066 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val);
1067 if (ret >= 0)
1068 hw_cfg->dout_hiz = val;
1069 else
1070 hw_cfg->dout_hiz = -1;
1071
1072 /* GPIO1 Pin Config */
1073 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert");
1074 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable");
1075 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val);
1076 if (ret >= 0) {
1077 gpio1->func = val;
1078 gpio1->valid = true;
1079 }
1080
1081 /* GPIO2 Pin Config */
1082 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert");
1083 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable");
1084 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val);
1085 if (ret >= 0) {
1086 gpio2->func = val;
1087 gpio2->valid = true;
1088 }
1089
1090 hw_cfg->valid = true;
1091
1092 return 0;
1093 }
1094
cs35l41_dsp_init(struct cs35l41_private * cs35l41)1095 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)
1096 {
1097 struct wm_adsp *dsp;
1098 uint32_t dsp1rx5_src;
1099 int ret;
1100
1101 dsp = &cs35l41->dsp;
1102 dsp->part = "cs35l41";
1103 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */
1104 dsp->toggle_preload = true;
1105
1106 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp);
1107
1108 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);
1109 if (ret < 0)
1110 return ret;
1111
1112 ret = wm_halo_init(dsp);
1113 if (ret) {
1114 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret);
1115 return ret;
1116 }
1117
1118 switch (cs35l41->hw_cfg.bst_type) {
1119 case CS35L41_INT_BOOST:
1120 case CS35L41_SHD_BOOST_ACTV:
1121 dsp1rx5_src = CS35L41_INPUT_SRC_VPMON;
1122 break;
1123 case CS35L41_EXT_BOOST:
1124 case CS35L41_SHD_BOOST_PASS:
1125 dsp1rx5_src = CS35L41_INPUT_SRC_VBSTMON;
1126 break;
1127 default:
1128 dev_err(cs35l41->dev, "wm_halo_init failed - Invalid Boost Type: %d\n",
1129 cs35l41->hw_cfg.bst_type);
1130 goto err_dsp;
1131 }
1132
1133 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, dsp1rx5_src);
1134 if (ret < 0) {
1135 dev_err(cs35l41->dev, "Write DSP1RX5_SRC: %d failed: %d\n", dsp1rx5_src, ret);
1136 goto err_dsp;
1137 }
1138 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, CS35L41_INPUT_SRC_VBSTMON);
1139 if (ret < 0) {
1140 dev_err(cs35l41->dev, "Write CS35L41_INPUT_SRC_VBSTMON failed: %d\n", ret);
1141 goto err_dsp;
1142 }
1143 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC,
1144 CS35L41_INPUT_SRC_TEMPMON);
1145 if (ret < 0) {
1146 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret);
1147 goto err_dsp;
1148 }
1149 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC,
1150 CS35L41_INPUT_SRC_RSVD);
1151 if (ret < 0) {
1152 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret);
1153 goto err_dsp;
1154 }
1155
1156 return 0;
1157
1158 err_dsp:
1159 wm_adsp2_remove(dsp);
1160
1161 return ret;
1162 }
1163
cs35l41_acpi_get_name(struct cs35l41_private * cs35l41)1164 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41)
1165 {
1166 acpi_handle handle = ACPI_HANDLE(cs35l41->dev);
1167 const char *sub;
1168
1169 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */
1170 if (!handle)
1171 return 0;
1172
1173 sub = acpi_get_subsystem_id(handle);
1174 if (IS_ERR(sub)) {
1175 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */
1176 if (PTR_ERR(sub) == -ENODATA)
1177 return 0;
1178 else
1179 return PTR_ERR(sub);
1180 }
1181
1182 cs35l41->dsp.system_name = sub;
1183 dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name);
1184
1185 return 0;
1186 }
1187
cs35l41_probe(struct cs35l41_private * cs35l41,const struct cs35l41_hw_cfg * hw_cfg)1188 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg)
1189 {
1190 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match;
1191 int irq_pol = 0;
1192 int ret;
1193
1194 if (hw_cfg) {
1195 cs35l41->hw_cfg = *hw_cfg;
1196 } else {
1197 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg);
1198 if (ret != 0)
1199 return ret;
1200 }
1201
1202 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++)
1203 cs35l41->supplies[i].supply = cs35l41_supplies[i];
1204
1205 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES,
1206 cs35l41->supplies);
1207 if (ret != 0) {
1208 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret);
1209 return ret;
1210 }
1211
1212 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1213 if (ret != 0) {
1214 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret);
1215 return ret;
1216 }
1217
1218 /* returning NULL can be an option if in stereo mode */
1219 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset",
1220 GPIOD_OUT_LOW);
1221 if (IS_ERR(cs35l41->reset_gpio)) {
1222 ret = PTR_ERR(cs35l41->reset_gpio);
1223 cs35l41->reset_gpio = NULL;
1224 if (ret == -EBUSY) {
1225 dev_info(cs35l41->dev,
1226 "Reset line busy, assuming shared reset\n");
1227 } else {
1228 dev_err(cs35l41->dev,
1229 "Failed to get reset GPIO: %d\n", ret);
1230 goto err;
1231 }
1232 }
1233 if (cs35l41->reset_gpio) {
1234 /* satisfy minimum reset pulse width spec */
1235 usleep_range(2000, 2100);
1236 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
1237 }
1238
1239 usleep_range(2000, 2100);
1240
1241 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4,
1242 int_status, int_status & CS35L41_OTP_BOOT_DONE,
1243 1000, 100000);
1244 if (ret) {
1245 dev_err(cs35l41->dev,
1246 "Failed waiting for OTP_BOOT_DONE: %d\n", ret);
1247 goto err;
1248 }
1249
1250 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status);
1251 if (int_status & CS35L41_OTP_BOOT_ERR) {
1252 dev_err(cs35l41->dev, "OTP Boot error\n");
1253 ret = -EINVAL;
1254 goto err;
1255 }
1256
1257 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id);
1258 if (ret < 0) {
1259 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret);
1260 goto err;
1261 }
1262
1263 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid);
1264 if (ret < 0) {
1265 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret);
1266 goto err;
1267 }
1268
1269 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK;
1270
1271 /* CS35L41 will have even MTLREVID
1272 * CS35L41R will have odd MTLREVID
1273 */
1274 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID;
1275 if (regid != chipid_match) {
1276 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n",
1277 regid, chipid_match);
1278 ret = -ENODEV;
1279 goto err;
1280 }
1281
1282 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1283
1284 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid);
1285 if (ret)
1286 goto err;
1287
1288 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap);
1289 if (ret < 0) {
1290 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret);
1291 goto err;
1292 }
1293
1294 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1295
1296 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg);
1297
1298 /* Set interrupt masks for critical errors */
1299 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,
1300 CS35L41_INT1_MASK_DEFAULT);
1301 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
1302 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
1303 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1304 0 << CS35L41_INT3_PLL_LOCK_SHIFT);
1305
1306 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq,
1307 IRQF_ONESHOT | IRQF_SHARED | irq_pol,
1308 "cs35l41", cs35l41);
1309 if (ret != 0) {
1310 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret);
1311 goto err;
1312 }
1313
1314 ret = cs35l41_set_pdata(cs35l41);
1315 if (ret < 0) {
1316 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret);
1317 goto err;
1318 }
1319
1320 ret = cs35l41_acpi_get_name(cs35l41);
1321 if (ret < 0)
1322 goto err;
1323
1324 ret = cs35l41_dsp_init(cs35l41);
1325 if (ret < 0)
1326 goto err;
1327
1328 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000);
1329 pm_runtime_use_autosuspend(cs35l41->dev);
1330 pm_runtime_mark_last_busy(cs35l41->dev);
1331 pm_runtime_set_active(cs35l41->dev);
1332 pm_runtime_get_noresume(cs35l41->dev);
1333 pm_runtime_enable(cs35l41->dev);
1334
1335 ret = devm_snd_soc_register_component(cs35l41->dev,
1336 &soc_component_dev_cs35l41,
1337 cs35l41_dai, ARRAY_SIZE(cs35l41_dai));
1338 if (ret < 0) {
1339 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret);
1340 goto err_pm;
1341 }
1342
1343 pm_runtime_put_autosuspend(cs35l41->dev);
1344
1345 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n",
1346 regid, reg_revid);
1347
1348 return 0;
1349
1350 err_pm:
1351 pm_runtime_dont_use_autosuspend(cs35l41->dev);
1352 pm_runtime_disable(cs35l41->dev);
1353 pm_runtime_put_noidle(cs35l41->dev);
1354
1355 wm_adsp2_remove(&cs35l41->dsp);
1356 err:
1357 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1358 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1359 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1360
1361 return ret;
1362 }
1363 EXPORT_SYMBOL_GPL(cs35l41_probe);
1364
cs35l41_remove(struct cs35l41_private * cs35l41)1365 void cs35l41_remove(struct cs35l41_private *cs35l41)
1366 {
1367 pm_runtime_get_sync(cs35l41->dev);
1368 pm_runtime_dont_use_autosuspend(cs35l41->dev);
1369 pm_runtime_disable(cs35l41->dev);
1370
1371 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
1372 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
1373 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
1374 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1375 1 << CS35L41_INT3_PLL_LOCK_SHIFT);
1376 kfree(cs35l41->dsp.system_name);
1377 wm_adsp2_remove(&cs35l41->dsp);
1378 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1379
1380 pm_runtime_put_noidle(cs35l41->dev);
1381
1382 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1383 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1384 }
1385 EXPORT_SYMBOL_GPL(cs35l41_remove);
1386
cs35l41_runtime_suspend(struct device * dev)1387 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev)
1388 {
1389 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1390
1391 dev_dbg(cs35l41->dev, "Runtime suspend\n");
1392
1393 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1394 return 0;
1395
1396 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1397
1398 regcache_cache_only(cs35l41->regmap, true);
1399 regcache_mark_dirty(cs35l41->regmap);
1400
1401 return 0;
1402 }
1403
cs35l41_runtime_resume(struct device * dev)1404 static int __maybe_unused cs35l41_runtime_resume(struct device *dev)
1405 {
1406 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1407 int ret;
1408
1409 dev_dbg(cs35l41->dev, "Runtime resume\n");
1410
1411 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1412 return 0;
1413
1414 regcache_cache_only(cs35l41->regmap, false);
1415
1416 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
1417 if (ret)
1418 return ret;
1419
1420 /* Test key needs to be unlocked to allow the OTP settings to re-apply */
1421 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1422 ret = regcache_sync(cs35l41->regmap);
1423 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1424 if (ret) {
1425 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret);
1426 return ret;
1427 }
1428 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg);
1429
1430 return 0;
1431 }
1432
cs35l41_sys_suspend(struct device * dev)1433 static int __maybe_unused cs35l41_sys_suspend(struct device *dev)
1434 {
1435 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1436
1437 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n");
1438 disable_irq(cs35l41->irq);
1439
1440 return 0;
1441 }
1442
cs35l41_sys_suspend_noirq(struct device * dev)1443 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev)
1444 {
1445 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1446
1447 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n");
1448 enable_irq(cs35l41->irq);
1449
1450 return 0;
1451 }
1452
cs35l41_sys_resume_noirq(struct device * dev)1453 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev)
1454 {
1455 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1456
1457 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n");
1458 disable_irq(cs35l41->irq);
1459
1460 return 0;
1461 }
1462
cs35l41_sys_resume(struct device * dev)1463 static int __maybe_unused cs35l41_sys_resume(struct device *dev)
1464 {
1465 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1466
1467 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n");
1468 enable_irq(cs35l41->irq);
1469
1470 return 0;
1471 }
1472
1473 const struct dev_pm_ops cs35l41_pm_ops = {
1474 SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL)
1475
1476 SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume)
1477 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq)
1478 };
1479 EXPORT_SYMBOL_GPL(cs35l41_pm_ops);
1480
1481 MODULE_DESCRIPTION("ASoC CS35L41 driver");
1482 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
1483 MODULE_LICENSE("GPL");
1484