Home
last modified time | relevance | path

Searched +full:0 +full:x00000020 (Results 1 – 25 of 1021) sorted by relevance

12345678910>>...41

/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-apalis-v1.1.dtsi17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18 brightness-levels = <0 45 63 88 119 158 203 255>;
28 pinctrl-0 = <&pinctrl_gpio8>;
30 gpio-fan,speed-map = < 0 0
82 pinctrl-0 = <&pinctrl_wifi_pdn>;
93 pinctrl-0 = <&pinctrl_gpio7>;
105 pinctrl-0 = <&pinctrl_usbh_en>;
135 reg = <0 0x84000000 0 0x2000000>;
140 reg = <0 0x86000000 0 0x200000>;
145 reg = <0 0x86200000 0 0x200000>;
[all …]
/openbmc/u-boot/board/freescale/mx6sxsabresd/
H A Dimximage.cfg33 DATA 4 0x020c4068 0xffffffff
34 DATA 4 0x020c406c 0xffffffff
35 DATA 4 0x020c4070 0xffffffff
36 DATA 4 0x020c4074 0xffffffff
37 DATA 4 0x020c4078 0xffffffff
38 DATA 4 0x020c407c 0xffffffff
39 DATA 4 0x020c4080 0xffffffff
40 DATA 4 0x020c4084 0xffffffff
43 DATA 4 0x020e0618 0x000c0000
44 DATA 4 0x020e05fc 0x00000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml116 reg = <0xc0100000 0x00000400>,
117 <0xc0101000 0x00000020>,
118 <0xc0102000 0x00000020>,
119 <0xc0103000 0x00000008>,
120 <0xc0104000 0x00000020>,
121 <0xc0105000 0x00000020>,
122 <0xc0106000 0x00000100>;
125 interrupts = <0 44 4>,<0 45 4>;
140 reg = <0x00001000 0x00000400>,
141 <0x00001460 0x00000020>,
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt39 - #size-cells: Must be <0>.
53 tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
55 reg = <0x00000001 0x00000000 0x00000400>,
56 <0x00000001 0x00000460 0x00000020>,
57 <0x00000001 0x00000480 0x00000020>,
58 <0x00000001 0x000004A0 0x00000008>,
59 <0x00000001 0x00000400 0x00000020>,
60 <0x00000001 0x00000420 0x00000020>;
63 interrupts = <0 41 4>, <0 40 4>;
77 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dcommon.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
43 #define PIPE_ID_PIPE_3D 0x00000000
44 #define PIPE_ID_PIPE_2D 0x00000001
45 #define SYNC_RECIPIENT_FE 0x00000001
46 #define SYNC_RECIPIENT_RA 0x00000005
47 #define SYNC_RECIPIENT_PE 0x00000007
48 #define SYNC_RECIPIENT_DE 0x0000000b
49 #define SYNC_RECIPIENT_BLT 0x00000010
50 #define ENDIAN_MODE_NO_SWAP 0x00000000
[all …]
/openbmc/u-boot/board/renesas/stout/
H A Dqos.c76 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init_es1()
80 writel(0x80FF1C1E, &s3c->s3cadsplcr); in qos_init_es1()
81 writel(0x1F060505, &s3c->s3crorr); in qos_init_es1()
82 writel(0x1F020100, &s3c->s3cworr); in qos_init_es1()
86 writel(0x00800080, &s3c_qos->s3cqos0); in qos_init_es1()
87 writel(0x22000010, &s3c_qos->s3cqos1); in qos_init_es1()
88 writel(0x22002200, &s3c_qos->s3cqos2); in qos_init_es1()
89 writel(0x2F002200, &s3c_qos->s3cqos3); in qos_init_es1()
90 writel(0x2F002F00, &s3c_qos->s3cqos4); in qos_init_es1()
91 writel(0x22000010, &s3c_qos->s3cqos5); in qos_init_es1()
[all …]
/openbmc/u-boot/board/renesas/lager/
H A Dqos.c74 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init_es1()
78 writel(0x80FF1C1E, &s3c->s3cadsplcr); in qos_init_es1()
79 writel(0x1F060505, &s3c->s3crorr); in qos_init_es1()
80 writel(0x1F020100, &s3c->s3cworr); in qos_init_es1()
84 writel(0x00800080, &s3c_qos->s3cqos0); in qos_init_es1()
85 writel(0x22000010, &s3c_qos->s3cqos1); in qos_init_es1()
86 writel(0x22002200, &s3c_qos->s3cqos2); in qos_init_es1()
87 writel(0x2F002200, &s3c_qos->s3cqos3); in qos_init_es1()
88 writel(0x2F002F00, &s3c_qos->s3cqos4); in qos_init_es1()
89 writel(0x22000010, &s3c_qos->s3cqos5); in qos_init_es1()
[all …]
/openbmc/u-boot/arch/nios2/dts/
H A D10m50_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
24 reg = <0x00000000>;
27 altr,exception-addr = <0xc8000120>;
28 altr,fast-tlb-miss-addr = <0xc0000100>;
35 altr,reset-addr = <0xd4000000>;
49 reg = <0x08000000 0x08000000>,
50 <0x00000000 0x00000400>;
53 sopc0: sopc@0 {
63 reg = <0x18001530 0x00000008>;
[all …]
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0x0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
/openbmc/linux/arch/nios2/boot/dts/
H A D3c120_devboard.dts18 #size-cells = <0>;
20 cpu: cpu@0 {
23 reg = <0x00000000>;
38 altr,reset-addr = <0xc2800000>;
39 altr,fast-tlb-miss-addr = <0xc7fff400>;
40 altr,exception-addr = <0xd0000020>;
46 memory@0 {
48 reg = <0x10000000 0x08000000>,
49 <0x07fff400 0x00000400>;
52 sopc@0 {
[all …]
H A D10m50_devboard.dts16 #size-cells = <0>;
18 cpu: cpu@0 {
21 reg = <0x00000000>;
24 altr,exception-addr = <0xc8000120>;
25 altr,fast-tlb-miss-addr = <0xc0000100>;
32 altr,reset-addr = <0xd4000000>;
46 reg = <0x08000000 0x08000000>,
47 <0x00000000 0x00000400>;
50 sopc0: sopc@0 {
60 reg = <0x18001530 0x00000008>;
[all …]
/openbmc/linux/arch/mips/ath25/
H A Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
29 #define AR2315_MISC_IRQ_UART0 0
43 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
44 #define AR2315_SPI_READ_SIZE 0x01000000
45 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
[all …]
/openbmc/u-boot/include/usb/
H A Ddesignware_udc.h35 #define ENDP_CNTL_STALL 0x00000001
36 #define ENDP_CNTL_FLUSH 0x00000002
37 #define ENDP_CNTL_SNOOP 0x00000004
38 #define ENDP_CNTL_POLL 0x00000008
39 #define ENDP_CNTL_CONTROL 0x00000000
40 #define ENDP_CNTL_ISO 0x00000010
41 #define ENDP_CNTL_BULK 0x00000020
42 #define ENDP_CNTL_INT 0x00000030
43 #define ENDP_CNTL_NAK 0x00000040
44 #define ENDP_CNTL_SNAK 0x00000080
[all …]
/openbmc/linux/sound/pci/cs46xx/
H A Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/openbmc/linux/drivers/net/ethernet/renesas/
H A Dravb.h38 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
41 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
45 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
49 CCC = 0x0000,
50 DBAT = 0x0004,
51 DLR = 0x0008,
[all …]
/openbmc/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dkeylargo.h10 /* "Pangea" chipset has keylargo device-id 0x25 while core99
11 * has device-id 0x22. The rev. of the pangea one is 0, so we
12 * fake an artificial rev. in keylargo_rev by oring 0x100
14 #define KL_PANGEA_REV 0x100
17 #define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
18 #define KEYLARGO_FCR0 0x38
19 #define KEYLARGO_FCR1 0x3c
20 #define KEYLARGO_FCR2 0x40
21 #define KEYLARGO_FCR3 0x44
22 #define KEYLARGO_FCR4 0x48
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Drfbuffer.h108 AR5K_RF_TURBO = 0,
165 #define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
168 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
169 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
171 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
172 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
174 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
175 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
181 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
182 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
[all …]
/openbmc/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.xml.h57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata_priv.h22 #define SATA_HOST_CAP_S64A 0x80000000
23 #define SATA_HOST_CAP_SNCQ 0x40000000
24 #define SATA_HOST_CAP_SSNTF 0x20000000
25 #define SATA_HOST_CAP_SMPS 0x10000000
26 #define SATA_HOST_CAP_SSS 0x08000000
27 #define SATA_HOST_CAP_SALP 0x04000000
28 #define SATA_HOST_CAP_SAL 0x02000000
29 #define SATA_HOST_CAP_SCLO 0x01000000
30 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
32 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl827c.h28 #define NV827C_SET_PRESENT_CONTROL (0x00000084)
30 #define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
31 #define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
32 #define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002)
36 #define NV827C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0…
37 #define NV827C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0
38 #define NV827C_SET_PROCESSING (0x00000110)
39 #define NV827C_SET_PROCESSING_USE_GAIN_OFS 0:0
40 #define NV827C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000)
41 #define NV827C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001)
[all …]
/openbmc/linux/sound/soc/fsl/
H A Dfsl_ssi.h15 /* SSI Transmit Data Register 0 */
16 #define REG_SSI_STX0 0x00
18 #define REG_SSI_STX1 0x04
19 /* SSI Receive Data Register 0 */
20 #define REG_SSI_SRX0 0x08
22 #define REG_SSI_SRX1 0x0c
24 #define REG_SSI_SCR 0x10
26 #define REG_SSI_SISR 0x14
28 #define REG_SSI_SIER 0x18
30 #define REG_SSI_STCR 0x1c
[all …]
/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
78 #define SPR_IMMUCR (SPRGROUP_IMMU + 0)
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
[all …]
/openbmc/u-boot/board/renesas/gose/
H A Dqos.c66 #define is_qos_pri_media() 0
72 #define is_qos_pri_normal() 0
78 #define is_qos_pri_gfx() 0
92 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
96 writel(0x00000000, &s3c->s3cadsplcr); in qos_init()
98 writel(0x1F0B0604, &s3c->s3crorr); in qos_init()
99 writel(0x1F0E0705, &s3c->s3cworr); in qos_init()
101 writel(0x1F0B0908, &s3c->s3crorr); in qos_init()
102 writel(0x1F0C0A08, &s3c->s3cworr); in qos_init()
104 writel(0x1F0B0B0B, &s3c->s3crorr); in qos_init()
[all …]
/openbmc/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]

12345678910>>...41