| /openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
| H A D | lcd.h | 14 u32 ssar; /* 0x00 Screen Start Address Register */
15 u32 sr; /* 0x04 LCD Size Register */
16 u32 vpw; /* 0x08 Virtual Page Width Register */
17 u32 cpr; /* 0x0C Cursor Position Register */
18 u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
19 u32 ccmr; /* 0x14 Color Cursor Mapping Register */
20 u32 pcr; /* 0x18 Panel Configuration Register */
21 u32 hcr; /* 0x1C Horizontal Configuration Register */
22 u32 vcr; /* 0x20 Vertical Configuration Register */
23 u32 por; /* 0x24 Panning Offset Register */
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_sh_mask.h | 26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
|
| /openbmc/u-boot/arch/arm/mach-omap2/omap3/ |
| H A D | clock.c | 55 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
111 *sys_clkin_sel = 0; in get_sys_clkin_sel()
136 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_34xx()
137 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, in dpll3_init_34xx()
141 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't in dpll3_init_34xx()
147 0x001F0000, (CORE_M3X2 + 1) << 16) ; in dpll3_init_34xx()
149 0x001F0000, CORE_M3X2 << 16); in dpll3_init_34xx()
153 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
157 0x07FF0000, ptr->m << 16); in dpll3_init_34xx()
161 0x00007F00, ptr->n << 8); in dpll3_init_34xx()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| H A D | smu_6_0_sh_mask.h | 26 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL
27 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
28 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L
29 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
30 #define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL
31 #define GPIOPAD_A__GPIO_A__SHIFT 0x00000000
32 #define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL
33 #define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000
34 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L
35 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/thermal/ |
| H A D | qoriq-thermal.yaml | 16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
|
| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | rtc.h | 14 u32 hourmin; /* 0x00 Hours and Minutes Counter Register */
15 u32 seconds; /* 0x04 Seconds Counter Register */
16 u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */
17 u32 alrm_sec; /* 0x0C Seconds Alarm Register */
18 u32 cr; /* 0x10 Control Register */
19 u32 isr; /* 0x14 Interrupt Status Register */
20 u32 ier; /* 0x18 Interrupt Enable Register */
21 u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
22 u32 days; /* 0x20 Days Counter Register */
23 u32 alrm_day; /* 0x24 Days Alarm Register */
[all …]
|
| /openbmc/u-boot/drivers/ata/ |
| H A D | dwc_ahsata_priv.h | 22 #define SATA_HOST_CAP_S64A 0x80000000
23 #define SATA_HOST_CAP_SNCQ 0x40000000
24 #define SATA_HOST_CAP_SSNTF 0x20000000
25 #define SATA_HOST_CAP_SMPS 0x10000000
26 #define SATA_HOST_CAP_SSS 0x08000000
27 #define SATA_HOST_CAP_SALP 0x04000000
28 #define SATA_HOST_CAP_SAL 0x02000000
29 #define SATA_HOST_CAP_SCLO 0x01000000
30 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
32 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/ |
| H A D | dce_6_0_sh_mask.h | 26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
|
| /openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | dram.c | 30 writel(0, &emc->config); in ddr_init()
32 writel(0x7FF, &emc->refresh); in ddr_init()
41 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
42 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
43 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); in ddr_init()
44 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); in ddr_init()
45 writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); in ddr_init()
46 writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc); in ddr_init()
47 writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); in ddr_init()
52 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
[all …]
|
| /openbmc/linux/arch/alpha/include/uapi/asm/ |
| H A D | termbits.h | 54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
[all …]
|
| /openbmc/linux/arch/arm/include/uapi/asm/ |
| H A D | ptrace.h | 37 #define PTRACE_GETFDPIC_EXEC 0
44 #define USR26_MODE 0x00000000
45 #define FIQ26_MODE 0x00000001
46 #define IRQ26_MODE 0x00000002
47 #define SVC26_MODE 0x00000003
50 * Use 0 here to get code right that creates a userspace
53 #define USR_MODE 0x00000000
54 #define SVC_MODE 0x00000000
56 #define USR_MODE 0x00000010
57 #define SVC_MODE 0x00000013
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| H A D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
|
| /openbmc/u-boot/board/is1/qts/ |
| H A D | iocsr_config.h | 15 0x00000000,
16 0x00000000,
17 0x0FF00000,
18 0xC0000000,
19 0x0000003F,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000000,
24 0x00018060,
[all …]
|
| /openbmc/linux/drivers/gpu/drm/etnaviv/ |
| H A D | state.xml.h | 7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000
49 #define VARYING_COMPONENT_USE_USED 0x00000001
50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
52 #define FE_DATA_TYPE_BYTE 0x00000000
53 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
54 #define FE_DATA_TYPE_SHORT 0x00000002
55 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
[all …]
|
| H A D | cmdstream.xml.h | 7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
|
| /openbmc/linux/drivers/media/pci/saa7164/ |
| H A D | saa7164-fw.c | 29 while ((saa7164_readl(reg) & 0x01) == 0) { in saa7164_dl_wait_ack()
31 if (timeout == 0) { in saa7164_dl_wait_ack()
39 return 0; in saa7164_dl_wait_ack()
45 while (saa7164_readl(reg) & 0x01) { in saa7164_dl_wait_clr()
47 if (timeout == 0) { in saa7164_dl_wait_clr()
55 return 0; in saa7164_dl_wait_clr()
74 "%s(image=%p, size=%d, flags=0x%x, dst=%p, dstsize=0x%x)\n", in saa7164_downloadimage()
95 dprintk(DBGLVL_FW, "%s() dlflag = 0x%x\n", __func__, dlflag); in saa7164_downloadimage()
96 dprintk(DBGLVL_FW, "%s() dlflag_ack = 0x%x\n", __func__, dlflag_ack); in saa7164_downloadimage()
97 dprintk(DBGLVL_FW, "%s() drflag = 0x%x\n", __func__, drflag); in saa7164_downloadimage()
[all …]
|
| /openbmc/linux/include/linux/ssb/ |
| H A D | ssb_driver_extif.h | 24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
[all …]
|
| /openbmc/linux/include/net/ |
| H A D | ieee80211_radiotap.h | 29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
|
| /openbmc/u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | sdram_arria10.h | 210 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
212 #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
214 #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
216 #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
218 #define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
220 #define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
222 #define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
223 #define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
231 #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
245 #define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
[all …]
|
| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | gm200.c | 41 pu &= 0x0f; in gm200_sor_dp_drive()
43 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in gm200_sor_dp_drive()
44 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in gm200_sor_dp_drive()
45 data[2] = nvkm_rd32(device, 0x61c130 + loff); in gm200_sor_dp_drive()
46 if ((data[2] & 0x00000f00) < (pu << 8) || ln == 0) in gm200_sor_dp_drive()
47 data[2] = (data[2] & ~0x00000f00) | (pu << 8); in gm200_sor_dp_drive()
49 nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift)); in gm200_sor_dp_drive()
50 nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift)); in gm200_sor_dp_drive()
51 nvkm_wr32(device, 0x61c130 + loff, data[2]); in gm200_sor_dp_drive()
53 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); in gm200_sor_dp_drive()
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/arch-omap3/ |
| H A D | clock.h | 19 #define FCK_IVA2_ON 0x00000001
20 #define FCK_CORE1_ON 0x03fffe29
21 #define ICK_CORE1_ON 0x3ffffffb
22 #define ICK_CORE2_ON 0x0000001f
23 #define FCK_WKUP_ON 0x000000e9
24 #define ICK_WKUP_ON 0x0000003f
25 #define FCK_DSS_ON 0x00000005
26 #define ICK_DSS_ON 0x00000001
27 #define FCK_CAM_ON 0x00000001
28 #define ICK_CAM_ON 0x00000001
|
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_1_0_sh_mask.h | 26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
|
| /openbmc/linux/drivers/staging/rtl8712/ |
| H A D | rtl8712_xmit.c | 73 case 0: in r8712_txframes_sta_ac_pending()
84 u32 addr = 0; in get_ff_hwaddr()
95 case 0: in get_ff_hwaddr()
111 case 0x10: in get_ff_hwaddr()
112 case 0x11: in get_ff_hwaddr()
113 case 0x12: in get_ff_hwaddr()
114 case 0x13: in get_ff_hwaddr()
123 case 0: in get_ff_hwaddr()
135 case 0x10: in get_ff_hwaddr()
136 case 0x11: in get_ff_hwaddr()
[all …]
|
| /openbmc/linux/arch/sparc/include/uapi/asm/ |
| H A D | psrcompat.h | 8 #define PSR_CWP 0x0000001f /* current window pointer */
9 #define PSR_ET 0x00000020 /* enable traps field */
10 #define PSR_PS 0x00000040 /* previous privilege level */
11 #define PSR_S 0x00000080 /* current privilege level */
12 #define PSR_PIL 0x00000f00 /* processor interrupt level */
13 #define PSR_EF 0x00001000 /* enable floating point */
14 #define PSR_EC 0x00002000 /* enable co-processor */
15 #define PSR_SYSCALL 0x00004000 /* inside of a syscall */
16 #define PSR_LE 0x00008000 /* SuperSparcII little-endian */
17 #define PSR_ICC 0x00f00000 /* integer condition codes */
[all …]
|
| /openbmc/linux/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_82575.h | 26 #define E1000_SW_SYNCH_MB 0x00000100
27 #define E1000_STAT_DEV_RST_SET 0x00100000
28 #define E1000_CTRL_DEV_RST 0x20000000
33 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
34 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
35 #define E1000_SRRCTL_DROP_EN 0x80000000
36 #define E1000_SRRCTL_TIMESTAMP 0x40000000
39 #define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
40 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
41 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
[all …]
|