Lines Matching +full:0 +full:x0000001f
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000
49 #define VARYING_COMPONENT_USE_USED 0x00000001
50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
52 #define FE_DATA_TYPE_BYTE 0x00000000
53 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
54 #define FE_DATA_TYPE_SHORT 0x00000002
55 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
56 #define FE_DATA_TYPE_INT 0x00000004
57 #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005
58 #define FE_DATA_TYPE_FLOAT 0x00000008
59 #define FE_DATA_TYPE_HALF_FLOAT 0x00000009
60 #define FE_DATA_TYPE_FIXED 0x0000000b
61 #define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c
62 #define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d
63 #define FE_DATA_TYPE_BYTE_I 0x0000000e
64 #define FE_DATA_TYPE_SHORT_I 0x0000000f
65 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff
66 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0
68 #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff0000
71 #define VIVS_FE 0x00000000
73 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0))
74 #define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE 0x00000004
75 #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010
76 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f
77 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0
79 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030
82 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE 0x00000080
83 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK 0x00000700
86 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK 0x00003000
89 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000
91 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000
92 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000
93 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000
96 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK 0xff000000
100 #define VIVS_FE_CMD_STREAM_BASE_ADDR 0x00000640
102 #define VIVS_FE_INDEX_STREAM_BASE_ADDR 0x00000644
104 #define VIVS_FE_INDEX_STREAM_CONTROL 0x00000648
105 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK 0x00000003
106 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT 0
107 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000
108 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001
109 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002
110 #define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100
112 #define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c
114 #define VIVS_FE_VERTEX_STREAM_CONTROL 0x00000650
116 #define VIVS_FE_COMMAND_ADDRESS 0x00000654
118 #define VIVS_FE_COMMAND_CONTROL 0x00000658
119 #define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff
120 #define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT 0
122 #define VIVS_FE_COMMAND_CONTROL_ENABLE 0x00010000
124 #define VIVS_FE_DMA_STATUS 0x0000065c
126 #define VIVS_FE_DMA_DEBUG_STATE 0x00000660
127 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK 0x0000001f
128 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT 0
129 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE 0x00000000
130 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC 0x00000001
131 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0 0x00000002
132 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0 0x00000003
133 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1 0x00000004
134 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1 0x00000005
135 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR 0x00000006
136 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD 0x00000007
137 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL 0x00000008
138 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL 0x00000009
139 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA 0x0000000a
140 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX 0x0000000b
141 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW 0x0000000c
142 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0 0x0000000d
143 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1 0x0000000e
144 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0 0x0000000f
145 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1 0x00000010
146 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO 0x00000011
147 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT 0x00000012
148 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK 0x00000013
149 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END 0x00000014
150 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL 0x00000015
151 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK 0x00000300
153 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE 0x00000000
154 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START 0x00000100
155 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ 0x00000200
156 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END 0x00000300
157 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK 0x00000c00
159 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE 0x00000000
160 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID 0x00000400
161 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID 0x00000800
162 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK 0x00003000
164 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE 0x00000000
165 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX 0x00001000
166 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL 0x00002000
167 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK 0x0000c000
169 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE 0x00000000
170 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR 0x00004000
171 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC 0x00008000
172 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK 0x00030000
174 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE 0x00000000
175 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE 0x00010000
176 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS 0x00020000
178 #define VIVS_FE_DMA_ADDRESS 0x00000664
180 #define VIVS_FE_DMA_LOW 0x00000668
182 #define VIVS_FE_DMA_HIGH 0x0000066c
184 #define VIVS_FE_AUTO_FLUSH 0x00000670
186 #define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674
188 #define VIVS_FE_UNK00678 0x00000678
190 #define VIVS_FE_UNK0067C 0x0000067c
192 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0))
193 #define VIVS_FE_VERTEX_STREAMS__ESIZE 0x00000004
194 #define VIVS_FE_VERTEX_STREAMS__LEN 0x00000008
196 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0))
198 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0))
200 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))
201 #define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004
202 #define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010
204 #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0))
206 #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0))
208 #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0))
210 #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0))
212 #define VIVS_FE_HALTI5_UNK007C4 0x000007c4
214 #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0))
215 #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004
216 #define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002
218 #define VIVS_FE_HALTI5_UNK007D8 0x000007d8
220 #define VIVS_FE_DESC_START 0x000007dc
222 #define VIVS_FE_DESC_END 0x000007e0
224 #define VIVS_FE_DESC_AVAIL 0x000007e4
225 #define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f
226 #define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0
229 #define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8
231 #define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4
233 #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8
235 #define VIVS_GL 0x00000000
237 #define VIVS_GL_PIPE_SELECT 0x00003800
238 #define VIVS_GL_PIPE_SELECT_PIPE__MASK 0x00000001
239 #define VIVS_GL_PIPE_SELECT_PIPE__SHIFT 0
242 #define VIVS_GL_EVENT 0x00003804
243 #define VIVS_GL_EVENT_EVENT_ID__MASK 0x0000001f
244 #define VIVS_GL_EVENT_EVENT_ID__SHIFT 0
246 #define VIVS_GL_EVENT_FROM_FE 0x00000020
247 #define VIVS_GL_EVENT_FROM_PE 0x00000040
248 #define VIVS_GL_EVENT_FROM_BLT 0x00000080
249 #define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00
253 #define VIVS_GL_SEMAPHORE_TOKEN 0x00003808
254 #define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK 0x0000001f
255 #define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT 0
257 #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00
260 #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000
264 #define VIVS_GL_FLUSH_CACHE 0x0000380c
265 #define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001
266 #define VIVS_GL_FLUSH_CACHE_COLOR 0x00000002
267 #define VIVS_GL_FLUSH_CACHE_TEXTURE 0x00000004
268 #define VIVS_GL_FLUSH_CACHE_PE2D 0x00000008
269 #define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010
270 #define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020
271 #define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040
272 #define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400
273 #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800
274 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000
275 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000
277 #define VIVS_GL_FLUSH_MMU 0x00003810
278 #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001
279 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK1 0x00000002
280 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK2 0x00000004
281 #define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU 0x00000008
282 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010
284 #define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814
286 #define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818
287 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003
288 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT 0
289 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE 0x00000000
290 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X 0x00000001
291 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X 0x00000002
292 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK 0x00000008
293 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK 0x000000f0
296 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK 0x00000100
297 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK 0x00007000
300 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK 0x00008000
301 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK 0x00030000
304 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK 0x00080000
306 #define VIVS_GL_VARYING_TOTAL_COMPONENTS 0x0000381c
307 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK 0x000000ff
308 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT 0
311 #define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820
313 #define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824
315 #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0))
316 #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004
317 #define VIVS_GL_VARYING_COMPONENT_USE__LEN 0x00000002
318 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK 0x00000003
319 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT 0
321 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK 0x0000000c
324 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK 0x00000030
327 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK 0x000000c0
330 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK 0x00000300
333 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK 0x00000c00
336 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK 0x00003000
339 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK 0x0000c000
342 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK 0x00030000
345 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK 0x000c0000
348 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK 0x00300000
351 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK 0x00c00000
354 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK 0x03000000
357 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK 0x0c000000
360 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK 0x30000000
363 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK 0xc0000000
367 #define VIVS_GL_UNK0382C 0x0000382c
369 #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830
371 #define VIVS_GL_UNK03834 0x00003834
373 #define VIVS_GL_UNK03838 0x00003838
375 #define VIVS_GL_API_MODE 0x0000384c
376 #define VIVS_GL_API_MODE_OPENGL 0x00000000
377 #define VIVS_GL_API_MODE_OPENVG 0x00000001
378 #define VIVS_GL_API_MODE_OPENCL 0x00000002
380 #define VIVS_GL_CONTEXT_POINTER 0x00003850
382 #define VIVS_GL_UNK03854 0x00003854
384 #define VIVS_GL_BUG_FIXES 0x00003860
386 #define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868
388 #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c
390 #define VIVS_GL_HALTI5_UNK03884 0x00003884
392 #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888
393 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f
394 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0
396 #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00
399 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000
402 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000
406 #define VIVS_GL_GS_UNK0388C 0x0000388c
408 #define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898
410 #define VIVS_GL_SHADER_INDEX 0x0000389c
412 #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0))
413 #define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004
414 #define VIVS_GL_GS_UNK038A0__LEN 0x00000008
416 #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0))
417 #define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004
418 #define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010
420 #define VIVS_GL_SECURITY_UNK3900 0x00003900
422 #define VIVS_GL_SECURITY_UNK3904 0x00003904
424 #define VIVS_GL_UNK03A00 0x00003a00
426 #define VIVS_GL_UNK03A04 0x00003a04
428 #define VIVS_GL_UNK03A08 0x00003a08
430 #define VIVS_GL_UNK03A0C 0x00003a0c
432 #define VIVS_GL_UNK03A10 0x00003a10
434 #define VIVS_GL_STALL_TOKEN 0x00003c00
435 #define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f
436 #define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0
438 #define VIVS_GL_STALL_TOKEN_TO__MASK 0x00001f00
441 #define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000
442 #define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000
444 #define VIVS_NFE 0x00000000
446 #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0))
447 #define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004
448 #define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010
450 #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0))
452 #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0))
454 #define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0))
456 #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0))
458 #define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))
459 #define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004
460 #define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020
462 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0))
463 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f
464 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0
466 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030
469 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700
472 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000
475 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000
477 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000
478 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000
479 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000
483 #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0))
485 #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0))
487 #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0))
489 #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0))
491 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0))
492 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff
493 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0
495 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800
497 #define VIVS_DUMMY 0x00000000
499 #define VIVS_DUMMY_DUMMY 0x0003fffc