Lines Matching +full:0 +full:x0000001f

55 	writel(0, &gpt1_base->tldr);		/* start counting at 0 */  in get_osc_clk_speed()
111 *sys_clkin_sel = 0; in get_sys_clkin_sel()
136 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_34xx()
137 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, in dpll3_init_34xx()
141 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't in dpll3_init_34xx()
147 0x001F0000, (CORE_M3X2 + 1) << 16) ; in dpll3_init_34xx()
149 0x001F0000, CORE_M3X2 << 16); in dpll3_init_34xx()
153 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
157 0x07FF0000, ptr->m << 16); in dpll3_init_34xx()
161 0x00007F00, ptr->n << 8); in dpll3_init_34xx()
164 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); in dpll3_init_34xx()
168 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_34xx()
171 0x00000030, CORE_FUSB_DIV << 4); in dpll3_init_34xx()
174 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_34xx()
177 0x00000003, CORE_L3_DIV); in dpll3_init_34xx()
180 0x00000007, GFX_DIV); in dpll3_init_34xx()
183 0x00000006, WKUP_RSM << 1); in dpll3_init_34xx()
186 0x000000F0, ptr->fsel << 4); in dpll3_init_34xx()
189 0x00000007, PLL_LOCK); in dpll3_init_34xx()
201 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_34xx()
203 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); in dpll3_init_34xx()
207 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
209 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); in dpll3_init_34xx()
211 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); in dpll3_init_34xx()
213 clrbits_le32(&p1, 0x00000040); in dpll3_init_34xx()
217 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_34xx()
219 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); in dpll3_init_34xx()
221 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_34xx()
223 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); in dpll3_init_34xx()
240 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); in dpll4_init_34xx()
241 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); in dpll4_init_34xx()
244 * Errata 1.50 Workaround for OMAP3 ES1.0 only in dpll4_init_34xx()
250 0x1F000000, (PER_M6X2 + 1) << 24); in dpll4_init_34xx()
252 0x1F000000, PER_M6X2 << 24); in dpll4_init_34xx()
254 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1)); in dpll4_init_34xx()
255 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2); in dpll4_init_34xx()
257 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1)); in dpll4_init_34xx()
258 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2); in dpll4_init_34xx()
261 0x00001F00, (PER_M3X2 + 1) << 8); in dpll4_init_34xx()
263 0x00001F00, PER_M3X2 << 8); in dpll4_init_34xx()
264 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ in dpll4_init_34xx()
265 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1)); in dpll4_init_34xx()
266 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_34xx()
271 0x0007FF00, ptr->m << 8); in dpll4_init_34xx()
273 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ in dpll4_init_34xx()
274 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); in dpll4_init_34xx()
277 clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20); in dpll4_init_34xx()
280 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); in dpll4_init_34xx()
293 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); in dpll5_init_34xx()
294 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_34xx()
296 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_34xx()
298 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); in dpll5_init_34xx()
300 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); in dpll5_init_34xx()
302 clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4); in dpll5_init_34xx()
304 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); in dpll5_init_34xx()
318 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ in mpu_init_34xx()
320 0x0000001F, ptr->m2); in mpu_init_34xx()
324 0x0007FF00, ptr->m << 8); in mpu_init_34xx()
326 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ in mpu_init_34xx()
328 0x0000007F, ptr->n); in mpu_init_34xx()
332 0x000000F0, ptr->fsel << 4); in mpu_init_34xx()
344 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ in iva_init_34xx()
346 0x00000007, PLL_STOP); in iva_init_34xx()
347 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); in iva_init_34xx()
349 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ in iva_init_34xx()
351 0x0000001F, ptr->m2); in iva_init_34xx()
355 0x0007FF00, ptr->m << 8); in iva_init_34xx()
357 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ in iva_init_34xx()
359 0x0000007F, ptr->n); in iva_init_34xx()
363 0x000000F0, ptr->fsel << 4); in iva_init_34xx()
365 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ in iva_init_34xx()
367 0x00000007, PLL_LOCK); in iva_init_34xx()
391 /* Select relock bypass: CM_CLKEN_PLL[0:2] */ in dpll3_init_36xx()
393 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_36xx()
394 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, in dpll3_init_36xx()
399 0x001F0000, CORE_M3X2 << 16); in dpll3_init_36xx()
403 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
407 0x07FF0000, ptr->m << 16); in dpll3_init_36xx()
411 0x00007F00, ptr->n << 8); in dpll3_init_36xx()
414 clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); in dpll3_init_36xx()
418 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_36xx()
421 0x00000030, CORE_FUSB_DIV << 4); in dpll3_init_36xx()
424 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_36xx()
427 0x00000003, CORE_L3_DIV); in dpll3_init_36xx()
430 0x00000007, GFX_DIV_36X); in dpll3_init_36xx()
433 0x00000006, WKUP_RSM << 1); in dpll3_init_36xx()
436 0x000000F0, ptr->fsel << 4); in dpll3_init_36xx()
439 0x00000007, PLL_LOCK); in dpll3_init_36xx()
451 clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_36xx()
453 clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); in dpll3_init_36xx()
457 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
459 clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); in dpll3_init_36xx()
461 clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); in dpll3_init_36xx()
463 clrbits_le32(&p1, 0x00000040); in dpll3_init_36xx()
467 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_36xx()
469 clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); in dpll3_init_36xx()
471 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_36xx()
473 clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); in dpll3_init_36xx()
492 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); in dpll4_init_36xx()
493 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); in dpll4_init_36xx()
496 clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24); in dpll4_init_36xx()
498 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */ in dpll4_init_36xx()
499 clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5); in dpll4_init_36xx()
501 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */ in dpll4_init_36xx()
502 clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4); in dpll4_init_36xx()
505 clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8); in dpll4_init_36xx()
507 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ in dpll4_init_36xx()
508 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_36xx()
511 clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8); in dpll4_init_36xx()
513 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ in dpll4_init_36xx()
514 clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); in dpll4_init_36xx()
517 clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12); in dpll4_init_36xx()
520 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); in dpll4_init_36xx()
533 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); in dpll5_init_36xx()
534 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); in dpll5_init_36xx()
536 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_36xx()
538 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8); in dpll5_init_36xx()
540 clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n); in dpll5_init_36xx()
542 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK); in dpll5_init_36xx()
556 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */ in mpu_init_36xx()
557 clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2); in mpu_init_36xx()
560 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8); in mpu_init_36xx()
562 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */ in mpu_init_36xx()
563 clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n); in mpu_init_36xx()
575 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */ in iva_init_36xx()
576 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP); in iva_init_36xx()
577 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); in iva_init_36xx()
579 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */ in iva_init_36xx()
580 clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2); in iva_init_36xx()
583 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8); in iva_init_36xx()
585 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */ in iva_init_36xx()
586 clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n); in iva_init_36xx()
588 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */ in iva_init_36xx()
589 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK); in iva_init_36xx()
600 u32 osc_clk = 0, sys_clkin_sel; in prcm_init()
601 u32 clk_index, sil_index = 0; in prcm_init()
613 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); in prcm_init()
618 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6); in prcm_init()
622 clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6); in prcm_init()
641 clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100); in prcm_init()
646 0x00000007, PLL_LOW_POWER_BYPASS); in prcm_init()
647 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, in prcm_init()
650 dpll3_init_36xx(0, clk_index); in prcm_init()
651 dpll4_init_36xx(0, clk_index); in prcm_init()
652 dpll5_init_36xx(0, clk_index); in prcm_init()
653 iva_init_36xx(0, clk_index); in prcm_init()
654 mpu_init_36xx(0, clk_index); in prcm_init()
658 0x00000007, PLL_LOCK); in prcm_init()
676 0x00000007, PLL_LOW_POWER_BYPASS); in prcm_init()
677 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, in prcm_init()
690 0x00000007, PLL_LOCK); in prcm_init()
696 setbits_le32(&prcm_base->clksel_per, 0x000000FF); in prcm_init()
715 setbits_le32(&prcm_base->fclken_usbhost, 0x00000003); in ehci_clocks_enable()
717 setbits_le32(&prcm_base->iclken3_core, 0x00000004); in ehci_clocks_enable()
719 setbits_le32(&prcm_base->fclken3_core, 0x00000004); in ehci_clocks_enable()
730 setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */ in per_clocks_enable()
731 setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */ in per_clocks_enable()
732 setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */ in per_clocks_enable()
735 setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */ in per_clocks_enable()
736 setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */ in per_clocks_enable()
737 setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */ in per_clocks_enable()
741 setbits_le32(&prcm_base->fclken1_core, 0x00002000); in per_clocks_enable()
742 setbits_le32(&prcm_base->iclken1_core, 0x00002000); in per_clocks_enable()
745 setbits_le32(&prcm_base->fclken1_core, 0x00004000); in per_clocks_enable()
746 setbits_le32(&prcm_base->iclken1_core, 0x00004000); in per_clocks_enable()
749 setbits_le32(&prcm_base->fclken_per, 0x00000800); in per_clocks_enable()
750 setbits_le32(&prcm_base->iclken_per, 0x00000800); in per_clocks_enable()
754 setbits_le32(&prcm_base->fclken_per, 0x00002000); in per_clocks_enable()
755 setbits_le32(&prcm_base->iclken_per, 0x00002000); in per_clocks_enable()
758 setbits_le32(&prcm_base->fclken_per, 0x00004000); in per_clocks_enable()
759 setbits_le32(&prcm_base->iclken_per, 0x00004000); in per_clocks_enable()
762 setbits_le32(&prcm_base->fclken_per, 0x00008000); in per_clocks_enable()
763 setbits_le32(&prcm_base->iclken_per, 0x00008000); in per_clocks_enable()
766 setbits_le32(&prcm_base->fclken_per, 0x00010000); in per_clocks_enable()
767 setbits_le32(&prcm_base->iclken_per, 0x00010000); in per_clocks_enable()
770 setbits_le32(&prcm_base->fclken_per, 0x00020000); in per_clocks_enable()
771 setbits_le32(&prcm_base->iclken_per, 0x00020000); in per_clocks_enable()
776 setbits_le32(&prcm_base->fclken1_core, 0x00038000); in per_clocks_enable()
777 setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */ in per_clocks_enable()
780 setbits_le32(&prcm_base->iclken_wkup, 0x00000004); in per_clocks_enable()