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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/openbmc/u-boot/board/k+p/kp_imx6q_tpc/
H A Dkp_imx6q_tpc_spl.c42 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
43 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
44 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
45 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
46 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
47 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
48 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
107 .dram_sdclk_0 = 0x00000030,
108 .dram_sdclk_1 = 0x00000030,
109 .dram_cas = 0x00000030,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-eckelmann-ci4x10.dts23 reg = <0x10000000 0x40000000>;
29 #clock-cells = <0>;
36 pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
48 pinctrl-0 = <&pinctrl_siox>;
58 pinctrl-0 = <&pinctrl_flexcan1>;
64 pinctrl-0 = <&pinctrl_flexcan2>;
77 pinctrl-0 = <&pinctrl_ecspi2>;
81 flash@0 {
83 reg = <0>;
90 pinctrl-0 = <&pinctrl_ecspi1>;
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar956x_initvals.h41 {0x00009800, 0xafe68e30},
42 {0x00009804, 0xfd14e000},
43 {0x00009808, 0x9c0a9f6b},
44 {0x0000980c, 0x04900000},
45 {0x00009814, 0x0280c00a},
46 {0x00009818, 0x00000000},
47 {0x0000981c, 0x00020028},
48 {0x00009834, 0x6400a190},
49 {0x00009838, 0x0108ecff},
50 {0x0000983c, 0x14000600},
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-ddr3-1600.dtsi8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80151015
18 0x14040902
[all …]
/openbmc/linux/arch/sh/include/cpu-sh4/cpu/
H A Ddma-register.h17 #define CHCR_TS_LOW_MASK 0x00000018
19 #define CHCR_TS_HIGH_MASK 0
20 #define CHCR_TS_HIGH_SHIFT 0
26 #define CHCR_TS_LOW_MASK 0x00000018
28 #define CHCR_TS_HIGH_MASK 0x00300000
34 #define CHCR_TS_LOW_MASK 0x00000018
36 #define CHCR_TS_HIGH_MASK 0x00100000
42 XMIT_SZ_8BIT = 0,
48 XMIT_SZ_128BIT_BLK = 0xb,
49 XMIT_SZ_256BIT_BLK = 0xc,
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/openbmc/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs35l45-tables.c15 { 0x00000040, 0x00000055 },
16 { 0x00000040, 0x000000AA },
17 { 0x00000044, 0x00000055 },
18 { 0x00000044, 0x000000AA },
19 { 0x00006480, 0x0830500A },
20 { 0x00007C60, 0x1000850B },
21 { CS35L45_BOOST_OV_CFG, 0x007000D0 },
22 { CS35L45_LDPM_CONFIG, 0x0001B636 },
23 { 0x00002C08, 0x00000009 },
24 { 0x00006850, 0x0A30FFC4 },
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_1_0_sh_mask.h26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A Dg94.c35 nvkm_mask(device, 0x001098, 0x00000008, 0x00000000); in g94_bus_hwsq_exec()
36 nvkm_wr32(device, 0x001304, 0x00000000); in g94_bus_hwsq_exec()
37 nvkm_wr32(device, 0x001318, 0x00000000); in g94_bus_hwsq_exec()
38 for (i = 0; i < size; i++) in g94_bus_hwsq_exec()
39 nvkm_wr32(device, 0x080000 + (i * 4), data[i]); in g94_bus_hwsq_exec()
40 nvkm_mask(device, 0x001098, 0x00000018, 0x00000018); in g94_bus_hwsq_exec()
41 nvkm_wr32(device, 0x00130c, 0x00000001); in g94_bus_hwsq_exec()
44 if (!(nvkm_rd32(device, 0x001308) & 0x00000100)) in g94_bus_hwsq_exec()
46 ) < 0) in g94_bus_hwsq_exec()
49 return 0; in g94_bus_hwsq_exec()
H A Dnv50.c36 nvkm_mask(device, 0x001098, 0x00000008, 0x00000000); in nv50_bus_hwsq_exec()
37 nvkm_wr32(device, 0x001304, 0x00000000); in nv50_bus_hwsq_exec()
38 for (i = 0; i < size; i++) in nv50_bus_hwsq_exec()
39 nvkm_wr32(device, 0x001400 + (i * 4), data[i]); in nv50_bus_hwsq_exec()
40 nvkm_mask(device, 0x001098, 0x00000018, 0x00000018); in nv50_bus_hwsq_exec()
41 nvkm_wr32(device, 0x00130c, 0x00000003); in nv50_bus_hwsq_exec()
44 if (!(nvkm_rd32(device, 0x001308) & 0x00000100)) in nv50_bus_hwsq_exec()
46 ) < 0) in nv50_bus_hwsq_exec()
49 return 0; in nv50_bus_hwsq_exec()
57 u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); in nv50_bus_intr()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/openbmc/linux/include/linux/amba/
H A Dclcd-regs.h17 #define CLCD_TIM0 0x00000000
18 #define CLCD_TIM1 0x00000004
19 #define CLCD_TIM2 0x00000008
20 #define CLCD_TIM3 0x0000000c
21 #define CLCD_UBAS 0x00000010
22 #define CLCD_LBAS 0x00000014
24 #define CLCD_PL110_IENB 0x00000018
25 #define CLCD_PL110_CNTL 0x0000001c
26 #define CLCD_PL110_STAT 0x00000020
27 #define CLCD_PL110_INTR 0x00000024
[all …]
/openbmc/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.xml.h57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/openbmc/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]
/openbmc/linux/sound/firewire/motu/
H A Dmotu-protocol-v1.c10 // Status register for MOTU 828 (0x'ffff'f000'0b00).
12 // 0xffff0000: ISOC_COMM_CONTROL_MASK in motu-stream.c.
13 // 0x00008000: mode of optical input interface.
14 // 0x00008000: for S/PDIF signal.
15 // 0x00000000: disabled or for ADAT signal.
16 // 0x00004000: mode of optical output interface.
17 // 0x00004000: for S/PDIF signal.
18 // 0x00000000: disabled or for ADAT signal.
19 // 0x00003f00: monitor input mode.
20 // 0x00000800: analog-1/2
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c19 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
20 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
21 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
22 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
23 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
24 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
25 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
26 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
27 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
36 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_phy_28nm_8960.xml.h56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
66 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
68 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
70 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
72 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
74 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
[all …]
/openbmc/linux/drivers/gpu/drm/pl111/
H A Dpl111_drm.h29 #define CLCD_TIM0 0x00000000
30 #define CLCD_TIM1 0x00000004
31 #define CLCD_TIM2 0x00000008
32 #define CLCD_TIM3 0x0000000c
33 #define CLCD_UBAS 0x00000010
34 #define CLCD_LBAS 0x00000014
36 #define CLCD_PL110_IENB 0x00000018
37 #define CLCD_PL110_CNTL 0x0000001c
38 #define CLCD_PL110_STAT 0x00000020
39 #define CLCD_PL110_INTR 0x00000024
[all …]

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