16a0abce4SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0 26a0abce4SKuninori Morimoto * 38b1935e6SGuennadi Liakhovetski * SH4 CPU-specific DMA definitions, used by both DMA drivers 48b1935e6SGuennadi Liakhovetski * 58b1935e6SGuennadi Liakhovetski * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 68b1935e6SGuennadi Liakhovetski */ 78b1935e6SGuennadi Liakhovetski #ifndef CPU_DMA_REGISTER_H 88b1935e6SGuennadi Liakhovetski #define CPU_DMA_REGISTER_H 98b1935e6SGuennadi Liakhovetski 108b1935e6SGuennadi Liakhovetski /* SH7751/7760/7780 DMA IRQ sources */ 118b1935e6SGuennadi Liakhovetski 128b1935e6SGuennadi Liakhovetski #ifdef CONFIG_CPU_SH4A 138b1935e6SGuennadi Liakhovetski 148b1935e6SGuennadi Liakhovetski #define DMAOR_INIT DMAOR_DME 158b1935e6SGuennadi Liakhovetski 169cdb81c7SNobuhiro Iwamatsu #if defined(CONFIG_CPU_SUBTYPE_SH7343) 178b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_MASK 0x00000018 188b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_SHIFT 3 198b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_MASK 0 208b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_SHIFT 0 21c8e3149bSGuennadi Liakhovetski #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 229cdb81c7SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 23050d4cc7SPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7724) || \ 249cdb81c7SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7730) || \ 25050d4cc7SPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7786) 268b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_MASK 0x00000018 278b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_SHIFT 3 288b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_MASK 0x00300000 298b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ 30ffe0e190SNobuhiro Iwamatsu #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ 31ffe0e190SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 32ffe0e190SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 33ffe0e190SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7785) 348ac53ed5SYoshihiro Shimoda #define CHCR_TS_LOW_MASK 0x00000018 358ac53ed5SYoshihiro Shimoda #define CHCR_TS_LOW_SHIFT 3 368ac53ed5SYoshihiro Shimoda #define CHCR_TS_HIGH_MASK 0x00100000 378ac53ed5SYoshihiro Shimoda #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ 388b1935e6SGuennadi Liakhovetski #endif 398b1935e6SGuennadi Liakhovetski 408b1935e6SGuennadi Liakhovetski /* Transmit sizes and respective CHCR register values */ 418b1935e6SGuennadi Liakhovetski enum { 428b1935e6SGuennadi Liakhovetski XMIT_SZ_8BIT = 0, 438b1935e6SGuennadi Liakhovetski XMIT_SZ_16BIT = 1, 448b1935e6SGuennadi Liakhovetski XMIT_SZ_32BIT = 2, 458b1935e6SGuennadi Liakhovetski XMIT_SZ_64BIT = 7, 468b1935e6SGuennadi Liakhovetski XMIT_SZ_128BIT = 3, 478b1935e6SGuennadi Liakhovetski XMIT_SZ_256BIT = 4, 488b1935e6SGuennadi Liakhovetski XMIT_SZ_128BIT_BLK = 0xb, 498b1935e6SGuennadi Liakhovetski XMIT_SZ_256BIT_BLK = 0xc, 508b1935e6SGuennadi Liakhovetski }; 518b1935e6SGuennadi Liakhovetski 528b1935e6SGuennadi Liakhovetski /* log2(size / 8) - used to calculate number of transfers */ 538b1935e6SGuennadi Liakhovetski #define TS_SHIFT { \ 548b1935e6SGuennadi Liakhovetski [XMIT_SZ_8BIT] = 0, \ 558b1935e6SGuennadi Liakhovetski [XMIT_SZ_16BIT] = 1, \ 568b1935e6SGuennadi Liakhovetski [XMIT_SZ_32BIT] = 2, \ 578b1935e6SGuennadi Liakhovetski [XMIT_SZ_64BIT] = 3, \ 588b1935e6SGuennadi Liakhovetski [XMIT_SZ_128BIT] = 4, \ 598b1935e6SGuennadi Liakhovetski [XMIT_SZ_256BIT] = 5, \ 608b1935e6SGuennadi Liakhovetski [XMIT_SZ_128BIT_BLK] = 4, \ 618b1935e6SGuennadi Liakhovetski [XMIT_SZ_256BIT_BLK] = 5, \ 628b1935e6SGuennadi Liakhovetski } 638b1935e6SGuennadi Liakhovetski 648b1935e6SGuennadi Liakhovetski #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \ 65c2fe3092SGuennadi Liakhovetski (((i) & 0xc) << CHCR_TS_HIGH_SHIFT)) 668b1935e6SGuennadi Liakhovetski 678b1935e6SGuennadi Liakhovetski #else /* CONFIG_CPU_SH4A */ 688b1935e6SGuennadi Liakhovetski 698b1935e6SGuennadi Liakhovetski #define DMAOR_INIT (0x8000 | DMAOR_DME) 708b1935e6SGuennadi Liakhovetski 718b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_MASK 0x70 728b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_SHIFT 4 738b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_MASK 0 748b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_SHIFT 0 758b1935e6SGuennadi Liakhovetski 768b1935e6SGuennadi Liakhovetski /* Transmit sizes and respective CHCR register values */ 778b1935e6SGuennadi Liakhovetski enum { 788b1935e6SGuennadi Liakhovetski XMIT_SZ_8BIT = 1, 798b1935e6SGuennadi Liakhovetski XMIT_SZ_16BIT = 2, 808b1935e6SGuennadi Liakhovetski XMIT_SZ_32BIT = 3, 818b1935e6SGuennadi Liakhovetski XMIT_SZ_64BIT = 0, 828b1935e6SGuennadi Liakhovetski XMIT_SZ_256BIT = 4, 838b1935e6SGuennadi Liakhovetski }; 848b1935e6SGuennadi Liakhovetski 858b1935e6SGuennadi Liakhovetski /* log2(size / 8) - used to calculate number of transfers */ 868b1935e6SGuennadi Liakhovetski #define TS_SHIFT { \ 878b1935e6SGuennadi Liakhovetski [XMIT_SZ_8BIT] = 0, \ 888b1935e6SGuennadi Liakhovetski [XMIT_SZ_16BIT] = 1, \ 898b1935e6SGuennadi Liakhovetski [XMIT_SZ_32BIT] = 2, \ 908b1935e6SGuennadi Liakhovetski [XMIT_SZ_64BIT] = 3, \ 918b1935e6SGuennadi Liakhovetski [XMIT_SZ_256BIT] = 5, \ 928b1935e6SGuennadi Liakhovetski } 938b1935e6SGuennadi Liakhovetski 948b1935e6SGuennadi Liakhovetski #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT) 958b1935e6SGuennadi Liakhovetski 968b1935e6SGuennadi Liakhovetski #endif /* CONFIG_CPU_SH4A */ 978b1935e6SGuennadi Liakhovetski 988b1935e6SGuennadi Liakhovetski #endif 99