| /openbmc/qemu/target/xtensa/core-dc233c/ |
| H A D | gdb-config.c.inc | 3 Copyright (c) 2003-2010 Tensilica Inc.
25 XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, 0, 0, 0, 0, 0, 0)
26 XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, 0, 0, 0, 0, 0, 0)
27 XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, 0, 0, 0, 0, 0, 0)
28 XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, 0, 0, 0, 0, 0, 0)
29 XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, 0, 0, 0, 0, 0, 0)
30 XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, 0, 0, 0, 0, 0, 0)
31 XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, 0, 0, 0, 0, 0, 0)
32 XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, 0, 0, 0, 0, 0, 0)
33 XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, 0, 0, 0, 0, 0, 0)
[all …]
|
| /openbmc/qemu/target/xtensa/core-dc232b/ |
| H A D | gdb-config.c.inc | 9 the Free Software Foundation; either version 2 of the License, or
20 Boston, MA 02110-1301, USA. */
22 XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc,
23 0, 0, 0, 0, 0, 0)
24 XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0,
25 0, 0, 0, 0, 0, 0)
26 XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1,
27 0, 0, 0, 0, 0, 0)
28 XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2,
29 0, 0, 0, 0, 0, 0)
[all …]
|
| /openbmc/qemu/target/xtensa/core-sample_controller/ |
| H A D | gdb-config.c.inc | 3 Copyright (c) 2003-2016 Tensilica Inc.
24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
[all …]
|
| /openbmc/qemu/target/xtensa/core-test_kc705_be/ |
| H A D | gdb-config.c.inc | 3 Copyright (c) 2003-2015 Tensilica Inc.
23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
[all …]
|
| /openbmc/linux/arch/x86/platform/ce4100/ |
| H A D | falconfalls.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
27 #address-cells = <1>;
[all …]
|
| /openbmc/qemu/target/xtensa/core-lx106/ |
| H A D | gdb-config.c.inc | 3 Copyright (c) 2003-2010 Tensilica Inc.
23 XTREG( 0, 0,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
[all …]
|
| /openbmc/qemu/target/xtensa/core-de233_fpu/ |
| H A D | gdb-config.c.inc | 3 Copyright (c) 2003-2020 Tensilica Inc.
23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
[all …]
|
| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | stv090x_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #define STV090x_MID 0xf100
16 #define STV090x_OFFST_MRELEASE_FIELD 0
19 #define STV090x_DACR1 0xf113
22 #define STV090x_OFFST_DACR1_VALUE_FIELD 0
25 #define STV090x_DACR2 0xf114
26 #define STV090x_OFFST_DACR2_VALUE_FIELD 0
29 #define STV090x_OUTCFG 0xf11c
39 #define STV090x_MODECFG 0xf11d
41 #define STV090x_IRQSTATUS3 0xf120
[all …]
|
| /openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/ |
| H A D | gdb-config.c.inc | 3 Copyright (c) 2003-2019 Tensilica Inc.
23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
[all …]
|
| /openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/ |
| H A D | taprio.json | 4 "name": "Add taprio Qdisc to multi-queue device (8 queues)",
15 …e 1: taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queues 1@0 1@0 1@0 base-time 1000000000 s…
16 "expExitCode": "0",
18 … "matchPattern": "qdisc taprio 1: root refcnt [0-9]+ tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2",
26 "name": "Add taprio Qdisc with multiple sched-entry",
37 … 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queues 1@0 1@0 1@0 base-time 1000000000 sched-entry S 01 300000 s…
38 "expExitCode": "0",
40 "matchPattern": "index [0-9]+ cmd S gatemask 0x[0-9]+ interval [0-9]+00000",
48 "name": "Add taprio Qdisc with txtime-delay",
59 …taprio num_tc 3 map 2 2 1 0 2 2 2 2 2 2 2 2 2 2 2 2 queues 1@0 1@0 1@0 base-time 1000000000 sched-…
[all …]
|
| /openbmc/qemu/include/libdecnumber/ |
| H A D | decDPD.h | 9 Software Foundation; either version 2, or (at your option) any later
29 02110-1301, USA. */
31 /* ------------------------------------------------------------------------ */
33 /* [Automatically generated -- do not edit. 2007.05.05] */
34 /* ------------------------------------------------------------------------ */
35 /* ------------------------------------------------------------------------ */
41 /* uint16_t BCD2DPD[2458]; -- BCD -> DPD (0x999 => 2457) */
42 /* uint16_t BIN2DPD[1000]; -- Bin -> DPD (999 => 2457) */
43 /* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
44 /* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
[all …]
|
| /openbmc/linux/drivers/gpu/drm/panel/ |
| H A D | panel-truly-nt35597.c | 1 // SPDX-License-Identifier: GPL-2.0
64 struct mipi_dsi_device *dsi[2];
78 { { 0xff, 0x20 }, 2 },
79 { { 0xfb, 0x01 }, 2 },
80 { { 0x00, 0x01 }, 2 },
81 { { 0x01, 0x55 }, 2 },
82 { { 0x02, 0x45 }, 2 },
83 { { 0x05, 0x40 }, 2 },
84 { { 0x06, 0x19 }, 2 },
85 { { 0x07, 0x1e }, 2 },
[all …]
|
| /openbmc/qemu/target/xtensa/core-dsp3400/ |
| H A D | gdb-config.c.inc | 3 Copyright (c) 2003-2010 Tensilica Inc.
23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
[all …]
|
| /openbmc/linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
10 #include <linux/clk-provider.h>
16 #include <linux/nvmem-consumer.h>
25 /* REG: 0x00 */
26 #define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0)
27 /* REG: 0x01 */
28 #define RK3228_BYPASS_RXSENSE_EN BIT(2)
30 #define RK3228_BYPASS_PLLPD_EN BIT(0)
31 /* REG: 0x02 */
[all …]
|
| /openbmc/linux/drivers/accel/habanalabs/goya/ |
| H A D | goya_security.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
12 * goya_set_block_as_protected - set the given block as protected
20 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; in goya_pb_set_block()
22 while (pb_addr & 0xFFF) { in goya_pb_set_block()
23 WREG32(pb_addr, 0); in goya_pb_set_block()
34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, in goya_init_mme_protection_bits()
35 mmMME_SBB_POWER_ECO2 = 0xDFF64; in goya_init_mme_protection_bits()
67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; in goya_init_mme_protection_bits()
68 word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2; in goya_init_mme_protection_bits()
[all …]
|
| /openbmc/linux/sound/firewire/dice/ |
| H A D | dice-weiss.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // dice-weiss.c - a part of driver for DICE based devices
13 // Weiss DAC202: 192kHz 2-channel DAC
15 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
16 .rx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
19 // Weiss MAN301: 192kHz 2-channel music archive network player
21 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
22 .rx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
25 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire nterface
27 .tx_pcm_chs = {{2, 2, 2}, {0, 0, 0} },
[all …]
|
| /openbmc/linux/arch/arm64/crypto/ |
| H A D | sha512-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
8 * it under the terms of the GNU General Public License version 2 as
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
17 .set .Lv\b\().2d, \b
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
29 .inst 0xcec08000 | .L\rd | (.L\rn << 5)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
[all …]
|
| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | gdb-config.c.inc | 3 Copyright (c) 2003-2015 Tensilica Inc.
24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
[all …]
|
| /openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2015 Cadence Design Systems Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
|
| /openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
35 #define XCHAL_CP_NUM 2 /* number of coprocessors */
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */
38 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
48 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
50 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
53 #define XCHAL_CP0_SA_SIZE 0
[all …]
|
| /openbmc/linux/arch/mips/kernel/ |
| H A D | mips-r2-to-r6-emul.c | 28 #include <asm/mips-r2-to-r6-emul.h>
59 int mipsr2_emulation = 0;
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
86 return 0; in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
95 return 0; in mipsr6_emul()
[all …]
|
| /openbmc/linux/arch/arm/mach-omap1/ |
| H A D | mux.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
15 #include <linux/soc/ti/omap1-io.h>
30 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
31 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
34 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
35 MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
36 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
37 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
[all …]
|
| /openbmc/u-boot/arch/xtensa/include/asm/arch-de212/ |
| H A D | tie.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * Copyright (C) 1999-2015 Cadence Design Systems Inc.
14 #define XCHAL_CP_NUM 0 /* number of coprocessors */
15 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
16 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
17 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
19 /* Save area for non-coprocessor optional and custom (TIE) state: */
24 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
37 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
38 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
[all …]
|
| /openbmc/u-boot/board/freescale/mpc8568mds/ |
| H A D | mpc8568mds.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
26 {4, 10, 1, 0, 2}, /* TxD0 */
27 {4, 9, 1, 0, 2}, /* TxD1 */
28 {4, 8, 1, 0, 2}, /* TxD2 */
29 {4, 7, 1, 0, 2}, /* TxD3 */
30 {4, 23, 1, 0, 2}, /* TxD4 */
31 {4, 22, 1, 0, 2}, /* TxD5 */
32 {4, 21, 1, 0, 2}, /* TxD6 */
33 {4, 20, 1, 0, 2}, /* TxD7 */
[all …]
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| /openbmc/u-boot/board/freescale/mpc8569mds/ |
| H A D | mpc8569mds.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2010 Freescale Semiconductor.
30 #include "../common/pq-mds-pib.h"
35 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
38 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
42 {2, 11, 2, 0, 1}, /* CLK12 */
43 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
44 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
45 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
46 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
[all …]
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