1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
26 	{4, 10, 1, 0, 2}, /* TxD0 */
27 	{4,  9, 1, 0, 2}, /* TxD1 */
28 	{4,  8, 1, 0, 2}, /* TxD2 */
29 	{4,  7, 1, 0, 2}, /* TxD3 */
30 	{4, 23, 1, 0, 2}, /* TxD4 */
31 	{4, 22, 1, 0, 2}, /* TxD5 */
32 	{4, 21, 1, 0, 2}, /* TxD6 */
33 	{4, 20, 1, 0, 2}, /* TxD7 */
34 	{4, 15, 2, 0, 2}, /* RxD0 */
35 	{4, 14, 2, 0, 2}, /* RxD1 */
36 	{4, 13, 2, 0, 2}, /* RxD2 */
37 	{4, 12, 2, 0, 2}, /* RxD3 */
38 	{4, 29, 2, 0, 2}, /* RxD4 */
39 	{4, 28, 2, 0, 2}, /* RxD5 */
40 	{4, 27, 2, 0, 2}, /* RxD6 */
41 	{4, 26, 2, 0, 2}, /* RxD7 */
42 	{4, 11, 1, 0, 2}, /* TX_EN */
43 	{4, 24, 1, 0, 2}, /* TX_ER */
44 	{4, 16, 2, 0, 2}, /* RX_DV */
45 	{4, 30, 2, 0, 2}, /* RX_ER */
46 	{4, 17, 2, 0, 2}, /* RX_CLK */
47 	{4, 19, 1, 0, 2}, /* GTX_CLK */
48 	{1, 31, 2, 0, 3}, /* GTX125 */
51 	{5, 10, 1, 0, 2}, /* TxD0 */
52 	{5,  9, 1, 0, 2}, /* TxD1 */
53 	{5,  8, 1, 0, 2}, /* TxD2 */
54 	{5,  7, 1, 0, 2}, /* TxD3 */
55 	{5, 23, 1, 0, 2}, /* TxD4 */
56 	{5, 22, 1, 0, 2}, /* TxD5 */
57 	{5, 21, 1, 0, 2}, /* TxD6 */
58 	{5, 20, 1, 0, 2}, /* TxD7 */
59 	{5, 15, 2, 0, 2}, /* RxD0 */
60 	{5, 14, 2, 0, 2}, /* RxD1 */
61 	{5, 13, 2, 0, 2}, /* RxD2 */
62 	{5, 12, 2, 0, 2}, /* RxD3 */
63 	{5, 29, 2, 0, 2}, /* RxD4 */
64 	{5, 28, 2, 0, 2}, /* RxD5 */
65 	{5, 27, 2, 0, 3}, /* RxD6 */
66 	{5, 26, 2, 0, 2}, /* RxD7 */
67 	{5, 11, 1, 0, 2}, /* TX_EN */
68 	{5, 24, 1, 0, 2}, /* TX_ER */
69 	{5, 16, 2, 0, 2}, /* RX_DV */
70 	{5, 30, 2, 0, 2}, /* RX_ER */
71 	{5, 17, 2, 0, 2}, /* RX_CLK */
72 	{5, 19, 1, 0, 2}, /* GTX_CLK */
73 	{1, 31, 2, 0, 3}, /* GTX125 */
74 	{4,  6, 3, 0, 2}, /* MDIO */
75 	{4,  5, 1, 0, 2}, /* MDC */
78 	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
79 	{2, 1, 1, 0, 2}, /* UART_RTS1 */
80 	{2, 2, 2, 0, 2}, /* UART_CTS1 */
81 	{2, 3, 2, 0, 2}, /* UART_SIN1 */
83 	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
107 	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);  in board_early_init_f()
108 	port_c->cpdir2 |= 0x0f000000;  in board_early_init_f()
109 	port_c->cppar2 &= ~0x0f000000;  in board_early_init_f()
110 	port_c->cppar2 |= 0x0a000000;  in board_early_init_f()
113 	return 0;  in board_early_init_f()
120 	return 0;  in checkboard()
136 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;  in local_bus_init()
138 	gur->lbiuiplldcr1 = 0x00078080;  in local_bus_init()
140 		gur->lbiuiplldcr0 = 0x7c0f1bf0;  in local_bus_init()
142 		gur->lbiuiplldcr0 = 0x6c0f1bf0;  in local_bus_init()
144 		gur->lbiuiplldcr0 = 0x5c0f1bf0;  in local_bus_init()
147 	lbc->lcrr |= 0x00030000;  in local_bus_init()
171 	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);  in lbc_sdram_init()
172 	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);  in lbc_sdram_init()
175 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;  in lbc_sdram_init()
178 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;  in lbc_sdram_init()
179 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;  in lbc_sdram_init()
183 	 * MPC8568 uses "new" 15-16 style addressing.  in lbc_sdram_init()
191 	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;  in lbc_sdram_init()
193 	*sdram_addr = 0xff;  in lbc_sdram_init()
200 	for (idx = 0; idx < 8; idx++) {  in lbc_sdram_init()
201 		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;  in lbc_sdram_init()
203 		*sdram_addr = 0xff;  in lbc_sdram_init()
209 	 * Issue 8 MODE-set command.  in lbc_sdram_init()
211 	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;  in lbc_sdram_init()
213 	*sdram_addr = 0xff;  in lbc_sdram_init()
220 	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;  in lbc_sdram_init()
222 	*sdram_addr = 0xff;  in lbc_sdram_init()
247  * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
257 	/*switch temporarily to I2C bus #2 */  in pib_init()
261 	val8 = 0x00;  in pib_init()
262 	i2c_write(0x23, 0x6, 1, &val8, 1);  in pib_init()
263 	i2c_write(0x23, 0x7, 1, &val8, 1);  in pib_init()
264 	val8 = 0xff;  in pib_init()
265 	i2c_write(0x23, 0x2, 1, &val8, 1);  in pib_init()
266 	i2c_write(0x23, 0x3, 1, &val8, 1);  in pib_init()
268 	val8 = 0x00;  in pib_init()
269 	i2c_write(0x26, 0x6, 1, &val8, 1);  in pib_init()
270 	val8 = 0x34;  in pib_init()
271 	i2c_write(0x26, 0x7, 1, &val8, 1);  in pib_init()
272 	val8 = 0xf9;  in pib_init()
273 	i2c_write(0x26, 0x2, 1, &val8, 1);  in pib_init()
274 	val8 = 0xff;  in pib_init()
275 	i2c_write(0x26, 0x3, 1, &val8, 1);  in pib_init()
277 	val8 = 0x00;  in pib_init()
278 	i2c_write(0x27, 0x6, 1, &val8, 1);  in pib_init()
279 	i2c_write(0x27, 0x7, 1, &val8, 1);  in pib_init()
280 	val8 = 0xff;  in pib_init()
281 	i2c_write(0x27, 0x2, 1, &val8, 1);  in pib_init()
282 	val8 = 0xef;  in pib_init()
283 	i2c_write(0x27, 0x3, 1, &val8, 1);  in pib_init()
293 	int first_free_busno = 0;  in pci_init_board()
299 	devdisr = in_be32(&gur->devdisr);  in pci_init_board()
300 	pordevsr = in_be32(&gur->pordevsr);  in pci_init_board()
301 	porpllsr = in_be32(&gur->porpllsr);  in pci_init_board()
325 			pci_arb ? "arbiter" : "external-arbiter",  in pci_init_board()
339 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */  in pci_init_board()
353 	return 0;  in ft_board_setup()