Lines Matching +full:0 +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2010 Freescale Semiconductor.
30 #include "../common/pq-mds-pib.h"
35 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
38 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
42 {2, 11, 2, 0, 1}, /* CLK12 */
43 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
44 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
45 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
46 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
47 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
48 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
49 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
50 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
51 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
52 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
53 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
54 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
57 {2, 16, 2, 0, 3}, /* CLK17 */
58 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
59 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
60 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
61 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
62 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
63 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
64 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
65 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
66 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
67 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
68 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
69 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
72 {2, 11, 2, 0, 1}, /* CLK12 */
73 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
74 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
75 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
76 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
77 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
78 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
79 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
80 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
81 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
82 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
83 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
84 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
87 {2, 16, 2, 0, 3}, /* CLK17 */
88 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
89 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
90 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
91 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
92 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
93 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
94 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
95 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
96 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
97 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
98 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
99 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
103 {2, 15, 2, 0, 1}, /* CLK16 */
104 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
105 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
106 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
107 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
108 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
109 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
112 {2, 15, 2, 0, 1}, /* CLK16 */
113 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
114 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
115 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
116 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
117 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
118 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
121 {2, 15, 2, 0, 1}, /* CLK16 */
122 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
123 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
124 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
125 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
126 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
127 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
130 {2, 15, 2, 0, 1}, /* CLK16 */
131 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
132 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
133 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
134 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
135 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
136 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
139 /* UART1 is muxed with QE PortF bit [9-12].*/
140 {5, 12, 2, 0, 3}, /* UART1_SIN */
141 {5, 9, 1, 0, 3}, /* UART1_SOUT */
142 {5, 10, 2, 0, 3}, /* UART1_CTS_B */
143 {5, 11, 1, 0, 2}, /* UART1_RTS_B */
146 {0, 19, 1, 0, 2}, /* QEUART_TX */
147 {1, 17, 2, 0, 3}, /* QEUART_RX */
148 {0, 25, 1, 0, 1}, /* QEUART_RTS */
149 {1, 23, 2, 0, 1}, /* QEUART_CTS */
152 {5, 3, 1, 0, 1}, /* USB_OE */
153 {5, 4, 1, 0, 2}, /* USB_TP */
154 {5, 5, 1, 0, 2}, /* USB_TN */
155 {5, 6, 2, 0, 2}, /* USB_RP */
156 {5, 7, 2, 0, 1}, /* USB_RX */
157 {5, 8, 2, 0, 1}, /* USB_RN */
158 {2, 4, 2, 0, 2}, /* CLK5 */
161 {4, 27, 3, 0, 1}, /* SPI_MOSI */
162 {4, 28, 3, 0, 1}, /* SPI_MISO */
163 {4, 29, 3, 0, 1}, /* SPI_CLK */
164 {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
166 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
187 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000); in board_early_init_f()
188 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; in board_early_init_f()
189 gur->plppar1 |= PLPPAR1_I2C2_VAL; in board_early_init_f()
190 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; in board_early_init_f()
191 gur->plpdir1 |= PLPDIR1_I2C2_VAL; in board_early_init_f()
196 return 0; in board_early_init_f()
202 const u8 flash_esel = 0; in board_early_init_r()
205 * Remap Boot flash to caching-inhibited in board_early_init_r()
209 /* Flush d-cache and invalidate i-cache of any FLASH data */ in board_early_init_r()
218 0, flash_esel, /* ts, esel */ in board_early_init_r()
221 return 0; in board_early_init_r()
228 return 0; in checkboard()
238 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); in fixed_sdram()
239 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
240 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
241 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
242 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
243 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
244 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
245 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); in fixed_sdram()
246 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); in fixed_sdram()
247 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); in fixed_sdram()
248 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); in fixed_sdram()
249 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); in fixed_sdram()
250 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
251 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); in fixed_sdram()
252 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); in fixed_sdram()
253 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); in fixed_sdram()
254 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); in fixed_sdram()
255 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); in fixed_sdram()
257 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); in fixed_sdram()
258 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); in fixed_sdram()
259 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); in fixed_sdram()
263 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); in fixed_sdram()
266 debug("DDR - 1st controller: memory initializing\n"); in fixed_sdram()
271 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { in fixed_sdram()
294 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; in local_bus_init()
296 out_be32(&gur->lbiuiplldcr1, 0x00078080); in local_bus_init()
298 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); in local_bus_init()
300 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); in local_bus_init()
302 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); in local_bus_init()
304 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); in local_bus_init()
314 if (off < 0) { in fdt_board_disable_serial()
332 * U-Boot anylonger).
349 hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); in esdhc_disables_uart0()
358 u32 portnum = 0; in fdt_board_fixup_qe_uart()
359 int off = -1; in fdt_board_fixup_qe_uart()
376 if (off < 0) { in fdt_board_fixup_qe_uart()
382 idx = fdt_getprop(blob, off, "cell-index", &len); in fdt_board_fixup_qe_uart()
383 if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2)) in fdt_board_fixup_qe_uart()
390 fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1); in fdt_board_fixup_qe_uart()
391 fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1); in fdt_board_fixup_qe_uart()
392 fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum)); in fdt_board_fixup_qe_uart()
406 return 0; in board_mmc_init()
419 clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, in board_mmc_init()
421 clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, in board_mmc_init()
429 clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, in board_mmc_init()
431 clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, in board_mmc_init()
443 int off = -1; in fdt_board_fixup_esdhc()
455 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); in fdt_board_fixup_esdhc()
456 if (off < 0) in fdt_board_fixup_esdhc()
459 idx = fdt_getprop(blob, off, "cell-index", &len); in fdt_board_fixup_esdhc()
470 if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { in fdt_board_fixup_esdhc()
471 off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); in fdt_board_fixup_esdhc()
472 if (off < 0) { in fdt_board_fixup_esdhc()
476 fdt_delprop(blob, off, "sdhci,1-bit-only"); in fdt_board_fixup_esdhc()
495 do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode", in fdt_board_fixup_qe_usb()
512 fsl_pcie_init_board(0); in pci_init_board()
526 nodeoff = -1; in ft_board_setup()
528 "ucc_geth")) >= 0) { in ft_board_setup()
529 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", in ft_board_setup()
531 if (err < 0) { in ft_board_setup()
532 printf("WARNING: could not set tx-clock-name %s.\n", in ft_board_setup()
540 if (err < 0) { in ft_board_setup()
541 printf("WARNING: could not set phy-connection-type " in ft_board_setup()
546 index = fdt_getprop(blob, nodeoff, "cell-index", 0); in ft_board_setup()
548 printf("WARNING: could not get cell-index of ucc\n"); in ft_board_setup()
552 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); in ft_board_setup()
554 printf("WARNING: could not get phy-handle of ucc\n"); in ft_board_setup()
559 if (off < 0) { in ft_board_setup()
565 val = 0x7 + *index; /* RMII phy address starts from 0x8 */ in ft_board_setup()
568 if (err < 0) { in ft_board_setup()
569 printf("WARNING: could not set reg for phy-handle " in ft_board_setup()
583 return 0; in ft_board_setup()