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/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Datmel_pio4.h1 /* SPDX-License-Identifier: GPL-2.0+ */
66 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) argument
67 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) argument
68 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) argument
/openbmc/u-boot/drivers/pinctrl/exynos/
H A Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include "pinctrl-exynos.h"
35 /* given a pin-name, return the address of pin config registers */
40 const struct samsung_pin_ctrl *pin_ctrl = priv->pin_ctrl; in pin_to_bank_base()
41 const struct samsung_pin_bank_data *bank_data = pin_ctrl->pin_banks; in pin_to_bank_base()
42 u32 nr_banks = pin_ctrl->nr_banks, idx = 0; in pin_to_bank_base()
46 * The format of the pin name is <bank name>-<pin_number>. in pin_to_bank_base()
47 * Example: gpa0-4 (gpa0 is the bank name and 4 is the pin number. in pin_to_bank_base()
49 while (pin_name[idx] != '-') { in pin_to_bank_base()
54 *pin = pin_name[++idx] - '0'; in pin_to_bank_base()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx6sll-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx6sll-iomuxc"
8 - fsl,pins: each entry consists of 6 integers and represents the mux and config
11 imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
12 the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
39 Refer to imx6sll-pinfunc.h in device tree source folder for all available
H A Dfsl,imx7ulp-pinctrl.txt10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
14 - compatible: "fsl,imx7ulp-iomuxc1".
15 - fsl,pins: Each entry consists of 5 integers which represents the mux
19 imx7ulp-pinfunc.h in the device tree source folder.
21 pull-up on this pin.
39 #include "imx7ulp-pinfunc.h"
43 compatible = "fsl,imx7ulp-iomuxc1";
H A Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
H A Dfsl,mxs-pinctrl.txt6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
20 information about pull-up. For this reason, even seemingly boolean values are
34 particular function, like SSP0 functioning as mmc0-8bit. That said, the
37 "pinctrl-*" phandle in client device node should only have one group node
41 Required subnode-properties:
42 - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
56 - reg: Should be the index of the group nodes for same function. This property
[all …]
H A Datmel,at91-pio4-pinctrl.txt7 - compatible:
8 "atmel,sama5d2-pinctrl"
9 "microchip,sama7g5-pinctrl"
10 - reg: base address and length of the PIO controller.
11 - interrupts: interrupt outputs from the controller, one for each bank.
12 - interrupt-controller: mark the device node as an interrupt controller.
13 - #interrupt-cells: should be two.
14 - gpio-controller: mark the device node as a gpio controller.
15 - #gpio-cells: should be two.
17 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
[all …]
H A Dmediatek,mt8192-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
[all …]
H A Dmediatek,mt65xx-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt2701-pinctrl
19 - mediatek,mt2712-pinctrl
20 - mediatek,mt6397-pinctrl
21 - mediatek,mt7623-pinctrl
22 - mediatek,mt8127-pinctrl
[all …]
H A Dfsl,imx25-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
22 Refer to imx25-pinfunc.h in device tree source folder for all available
H A Dmediatek,mt6779-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Teng <andy.teng@mediatek.com>
11 - Sean Wang <sean.wang@kernel.org>
20 - mediatek,mt6779-pinctrl
21 - mediatek,mt6797-pinctrl
26 reg-names: true
28 gpio-controller: true
[all …]
H A Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
[all …]
H A Dmediatek,mt6795-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Sean Wang <sean.wang@kernel.org>
18 const: mediatek,mt6795-pinctrl
20 gpio-controller: true
22 '#gpio-cells':
29 gpio-ranges:
[all …]
H A Dfsl,imx51-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx51-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx51 datasheet for the valid pad
31 Refer to imx51-pinfunc.h in device tree source folder for all available
H A Dfsl,imx50-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx50-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx50 datasheet for the valid pad
31 Refer to imx50-pinfunc.h in device tree source folder for all available
H A Dfsl,imx53-pinctrl.txt3 Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
7 - compatible: "fsl,imx53-iomuxc"
8 - fsl,pins: two integers array, represents a group of pins mux and config
11 pull-up for this pin. Please refer to imx53 datasheet for the valid pad
31 Refer to imx53-pinfunc.h in device tree source folder for all available
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Datmel,at91-pio4-pinctrl.txt7 - compatible: "atmel,sama5d2-pinctrl".
8 - reg: base address and length of the PIO controller.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
23 - pinmux: integer array. Each integer represents a pin number plus mux and
24 ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the
28 - GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
29 bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
30 input-debounce.
34 #include <sama5d2-pinfunc.h>
39 cs-gpios = <&pioA 17 0>, <0>, <0>, <0>;
[all …]
H A Dst,stm32-pinctrl.txt5 also provides ability to multiplex and configure the output of various on-chip
10 - compatible: value should be one of the following:
11 (a) "st,stm32f429-pinctrl"
12 (b) "st,stm32f746-pinctrl"
13 - #address-cells: The value of this property must be 1
14 - #size-cells : The value of this property must be 1
15 - ranges : defines mapping between pin controller node (parent) to
16 gpio-bank node (children).
17 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
22 - gpio-controller : Indicates this device is a GPIO controller
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/pinctrl/at91.h>
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
72 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) argument
73 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) argument
74 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) argument
80 * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
107 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
157 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
[all …]
H A Dpinctrl-apple-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Based on: pinctrl-pistachio.c
13 #include <dt-bindings/pinctrl/apple.h>
29 #include "pinctrl-utils.h"
80 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
84 regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value); in apple_gpio_set_reg()
93 ret = regmap_read(pctl->map, REG_GPIO(pin), &val); in apple_gpio_get_reg()
109 u32 pinfunc, pin, func; in apple_gpio_dt_node_to_map() local
122 dev_err(pctl->dev, in apple_gpio_dt_node_to_map()
125 return ret ? ret : -EINVAL; in apple_gpio_dt_node_to_map()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include "imx6ull-pinfunc.h"
7 #include "imx6ull-pinfunc-snvs.h"
9 /* Delete UART8 in AIPS-1 (i.MX6UL specific) */
10 /delete-node/ &uart8;
11 /* Delete CAAM node in AIPS-2 (i.MX6UL specific) */
12 /delete-node/ &crypto;
15 clock-frequency = <900000000>;
16 operating-points = <
24 fsl,soc-operating-points = <
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192-asurada-audio-rt1015p.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
10 rt1015p: audio-codec {
12 pinctrl-names = "default";
13 pinctrl-0 = <&rt1015p_pins>;
14 sdb-gpios = <&pio 147 GPIO_ACTIVE_HIGH>;
15 #sound-dai-cells = <0>;
20 rt1015p_pins: rt1015p-default-pins {
23 output-low;
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * - GPIO4_0 rs485_en needs to be driven low (in-active)
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 compatible = "gw,imx8mm-gw73xx-0x";
24 gpio-hog;
26 output-low;
[all …]
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * - GPIO4_0 rs485_en needs to be driven low (in-active)
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 compatible = "gw,imx8mm-gw72xx-0x";
24 gpio-hog;
26 output-low;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-phycore-stm32mp1-3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
12 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include "stm32mp157c-phycore-stm32mp15-som.dtsi"
16 model = "PHYTEC phyCORE-STM32MP1-3 Dev Board";
17 compatible = "phytec,phycore-stm32mp1-3",
18 "phytec,phycore-stm32mp157c-som", "st,stm32mp157";

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