Home
last modified time | relevance | path

Searched +full:- +full:s (Results 1 – 25 of 1198) sorted by relevance

12345678910>>...48

/openbmc/qemu/scripts/
H A Dmeson-buildoptions.sh1 # This file is generated by meson-buildoptions.py, do not edit!
3 printf "%s\n" ' --audio-drv-list=CHOICES Set audio driver list [default] (choices: alsa/co'
4 printf "%s\n" ' reaudio/default/dsound/jack/oss/pa/pipewire/sdl/s'
5 printf "%s\n" ' ndio)'
6 printf "%s\n" ' --bindir=VALUE Executable directory [bin]'
7 printf "%s\n" ' --block-drv-ro-whitelist=VALUE'
8 printf "%s\n" ' set block driver read-only whitelist (by default'
9 printf "%s\n" ' affects only QEMU, not tools like qemu-img)'
10 printf "%s\n" ' --block-drv-rw-whitelist=VALUE'
11 printf "%s\n" ' set block driver read-write whitelist (by default'
[all …]
/openbmc/qemu/hw/scsi/
H A Desp.c4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Copyright (c) 2023 Mark Cave-Ayland
39 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
46 static void esp_raise_irq(ESPState *s) in esp_raise_irq() argument
48 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { in esp_raise_irq()
49 s->rregs[ESP_RSTAT] |= STAT_INT; in esp_raise_irq()
50 qemu_irq_raise(s->irq); in esp_raise_irq()
55 static void esp_lower_irq(ESPState *s) in esp_lower_irq() argument
57 if (s->rregs[ESP_RSTAT] & STAT_INT) { in esp_lower_irq()
[all …]
H A Dlsi53c895a.c13 * as well-behaved operating systems will not try to use them.
304 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
332 static inline int lsi_irq_on_rsl(LSIState *s) in lsi_irq_on_rsl() argument
334 return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE); in lsi_irq_on_rsl()
337 static lsi_request *get_pending_req(LSIState *s) in get_pending_req() argument
341 QTAILQ_FOREACH(p, &s->queue, next) { in get_pending_req()
342 if (p->pending) { in get_pending_req()
349 static void lsi_soft_reset(LSIState *s) in lsi_soft_reset() argument
352 s->carry = 0; in lsi_soft_reset()
354 s->msg_action = LSI_MSG_ACTION_COMMAND; in lsi_soft_reset()
[all …]
/openbmc/qemu/hw/audio/
H A Dsb16.c4 * Copyright (c) 2003-2005 Vassili Karpov (malc)
30 #include "hw/qdev-properties.h"
33 #include "qemu/host-utils.h"
153 return -1; in irq_of_magic()
160 ldebug ("%s:%s:%d:%s:dmasize=%d:freq=%d:const=%d:speaker=%d\n",
161 dsp->fmt_stereo ? "Stereo" : "Mono",
162 dsp->fmt_signed ? "Signed" : "Unsigned",
163 dsp->fmt_bits,
164 dsp->dma_auto ? "Auto" : "Single",
165 dsp->block_size,
[all …]
H A Dwm8750.c60 /* pow(10.0, -i / 20.0) * 255, i = 0..42 */
67 #define WM8750_OUTVOL_TRANSFORM(x) wm8750_vol_db_table[(0x7f - x) / 3]
70 static inline void wm8750_in_load(WM8750State *s) in wm8750_in_load() argument
72 if (s->idx_in + s->req_in <= sizeof(s->data_in)) in wm8750_in_load()
74 s->idx_in = MAX(0, (int) sizeof(s->data_in) - s->req_in); in wm8750_in_load()
75 AUD_read(*s->in[0], s->data_in + s->idx_in, in wm8750_in_load()
76 sizeof(s->data_in) - s->idx_in); in wm8750_in_load()
79 static inline void wm8750_out_flush(WM8750State *s) in wm8750_out_flush() argument
82 while (sent < s->idx_out) in wm8750_out_flush()
83 sent += AUD_write(*s->out[0], s->data_out + sent, s->idx_out - sent) in wm8750_out_flush()
[all …]
/openbmc/qemu/hw/i2c/
H A Dnpcm7xx_smbus.c22 #include "qemu/guest-random.h"
164 #define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) argument
165 #define NPCM7XX_SMBUS_FIFO_ENABLED(s) ((s)->fif_ctl & \ argument
168 /* VERSION fields values, read-only. */
200 static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) in npcm7xx_smbus_update_irq() argument
204 if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { in npcm7xx_smbus_update_irq()
205 level = !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && in npcm7xx_smbus_update_irq()
206 s->st & NPCM7XX_SMBST_NMATCH) || in npcm7xx_smbus_update_irq()
207 (s->st & NPCM7XX_SMBST_BER) || in npcm7xx_smbus_update_irq()
208 (s->st & NPCM7XX_SMBST_NEGACK) || in npcm7xx_smbus_update_irq()
[all …]
H A Dpm_smbus.c68 static void smb_transaction(PMSMBus *s) in smb_transaction() argument
70 uint8_t prot = (s->smb_ctl >> 2) & 0x07; in smb_transaction()
71 uint8_t read = s->smb_addr & 0x01; in smb_transaction()
72 uint8_t cmd = s->smb_cmd; in smb_transaction()
73 uint8_t addr = s->smb_addr >> 1; in smb_transaction()
74 I2CBus *bus = s->smbus; in smb_transaction()
79 if ((s->smb_stat & STS_DEV_ERR) != 0) { in smb_transaction()
100 ret = smbus_write_byte(bus, addr, cmd, s->smb_data0); in smb_transaction()
110 (s->smb_data1 << 8) | s->smb_data0); in smb_transaction()
115 /* According to the Linux i2c-i801 driver: in smb_transaction()
[all …]
/openbmc/qemu/hw/net/
H A Ddp8393x.c4 * Copyright (c) 2008-2009 Herve Poussineau
22 #include "hw/qdev-properties.h"
148 * signed 32 bit integer that might get sign-extended to a 64 bit integer.
150 static uint32_t dp8393x_cdp(dp8393xState *s) in dp8393x_cdp() argument
152 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; in dp8393x_cdp()
155 static uint32_t dp8393x_crba(dp8393xState *s) in dp8393x_crba() argument
157 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; in dp8393x_crba()
160 static uint32_t dp8393x_crda(dp8393xState *s) in dp8393x_crda() argument
162 return (s->regs[SONIC_URDA] << 16) | in dp8393x_crda()
163 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); in dp8393x_crda()
[all …]
H A Dlan9118.c9 * Contributions after 2012-01-13 are licensed under the terms of the
22 #include "hw/qdev-properties.h"
39 /* The tx and rx fifo ports are a range of aliased 32-bit registers */
330 static void lan9118_update(lan9118_state *s) in lan9118_update() argument
335 level = (s->int_sts & s->int_en) != 0; in lan9118_update()
337 s->irq_cfg |= IRQ_INT; in lan9118_update()
339 s->irq_cfg &= ~IRQ_INT; in lan9118_update()
341 if ((s->irq_cfg & IRQ_EN) == 0) { in lan9118_update()
344 if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) { in lan9118_update()
346 * active-high polarity, push-pull type. in lan9118_update()
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvvk.c.inc2 * RISC-V translation routines for the vector crypto extension.
25 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
27 if (CHECK(s, a)) { \
28 return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
29 gen_helper_##NAME, s); \
34 static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a)
36 return opivv_check(s, a) &&
37 s->cfg_ptr->ext_zvbc == true &&
38 s->sew == MO_64;
45 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
[all …]
/openbmc/qemu/hw/ide/
H A Dcore.c2 * QEMU IDE disk and CD/DVD-ROM Emulator
30 #include "qemu/error-report.h"
31 #include "qemu/main-loop.h"
33 #include "qemu/hw-version.h"
39 #include "system/block-backend.h"
44 #include "ide-internal.h"
63 /* airflow-temperature-celsius */
82 static void ide_dummy_transfer_stop(IDEState *s);
113 static void ide_identify_size(IDEState *s) in ide_identify_size() argument
115 uint16_t *p = (uint16_t *)s->identify_data; in ide_identify_size()
[all …]
/openbmc/qemu/hw/sd/
H A Dsdhci.c10 * Based on MMC controller for Samsung S5PC1xx-based board emulation
29 #include "qemu/error-report.h"
32 #include "hw/qdev-properties.h"
38 #include "sdhci-internal.h"
43 #define TYPE_SDHCI_BUS "sdhci-bus"
50 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) in DECLARE_INSTANCE_CHECKER()
52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); in DECLARE_INSTANCE_CHECKER()
56 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, in sdhci_check_capab_freq_range() argument
59 if (s->sd_spec_version >= 3) { in sdhci_check_capab_freq_range()
67 error_setg(errp, "SD %s clock frequency can have value" in sdhci_check_capab_freq_range()
[all …]
/openbmc/qemu/tests/qtest/
H A Dam53c974-test.c4 * Copyright (c) 2021 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
7 * later. See the COPYING file in the top-level directory.
17 QTestState *s = qtest_init( in test_cmdfifo_underflow_ok() local
18 "-device am53c974,id=scsi " in test_cmdfifo_underflow_ok()
19 "-device scsi-hd,drive=disk0 -drive " in test_cmdfifo_underflow_ok()
20 "id=disk0,if=none,file=null-co://,format=raw -nodefaults"); in test_cmdfifo_underflow_ok()
21 qtest_outl(s, 0xcf8, 0x80001004); in test_cmdfifo_underflow_ok()
22 qtest_outw(s, 0xcfc, 0x01); in test_cmdfifo_underflow_ok()
23 qtest_outl(s, 0xcf8, 0x8000100e); in test_cmdfifo_underflow_ok()
24 qtest_outl(s, 0xcfc, 0x8a000000); in test_cmdfifo_underflow_ok()
[all …]
/openbmc/qemu/hw/char/
H A Dserial.c4 * Copyright (c) 2003-2004 Fabrice Bellard
31 #include "chardev/char-serial.h"
36 #include "qemu/error-report.h"
38 #include "hw/qdev-properties.h"
39 #include "hw/qdev-properties-system.h"
83 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
89 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
91 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for eac…
106 static void serial_xmit(SerialState *s);
108 static inline void recv_fifo_put(SerialState *s, uint8_t chr) in recv_fifo_put() argument
[all …]
H A Dibex_uart.c31 #include "hw/qdev-clock.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
77 static void ibex_uart_update_irqs(IbexUartState *s) in ibex_uart_update_irqs() argument
79 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) { in ibex_uart_update_irqs()
80 qemu_set_irq(s->tx_watermark, 1); in ibex_uart_update_irqs()
82 qemu_set_irq(s->tx_watermark, 0); in ibex_uart_update_irqs()
85 if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) { in ibex_uart_update_irqs()
86 qemu_set_irq(s->rx_watermark, 1); in ibex_uart_update_irqs()
88 qemu_set_irq(s->rx_watermark, 0); in ibex_uart_update_irqs()
[all …]
/openbmc/qemu/hw/arm/
H A Dstrongarm.c2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
11 * Copyright (c) 2003-2004 Fabrice Bellard
26 * Contributions after 2012-01-13 are licensed under the terms of the
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
37 #include "qemu/error-report.h"
39 #include "chardev/char-fe.h"
40 #include "chardev/char-serial.h"
48 #include "target/arm/cpu-qom.h"
[all …]
/openbmc/qemu/hw/timer/
H A Dnrf51_timer.c2 * nRF51 System-on-Chip Timer peripheral
7 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
11 * the COPYING file in the top-level directory.
20 #include "hw/qdev-properties.h"
28 static uint32_t ns_to_ticks(NRF51TimerState *s, int64_t ns) in ns_to_ticks() argument
30 uint32_t freq = TIMER_CLK_FREQ >> s->prescaler; in ns_to_ticks()
35 static int64_t ticks_to_ns(NRF51TimerState *s, uint32_t ticks) in ticks_to_ns() argument
37 uint32_t freq = TIMER_CLK_FREQ >> s->prescaler; in ticks_to_ns()
43 static uint32_t update_counter(NRF51TimerState *s, int64_t now) in update_counter() argument
45 uint32_t ticks = ns_to_ticks(s, now - s->update_counter_ns); in update_counter()
[all …]
H A Dsh_timer.c6 * Copyright (c) 2005-2006 CodeSourcery.
52 static void sh_timer_update(SHTimerState *s) in sh_timer_update() argument
54 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); in sh_timer_update()
56 if (new_level != s->old_level) { in sh_timer_update()
57 qemu_set_irq(s->irq, new_level); in sh_timer_update()
59 s->old_level = s->int_level; in sh_timer_update()
60 s->int_level = new_level; in sh_timer_update()
65 SHTimerState *s = opaque; in sh_timer_read() local
69 return s->tcor; in sh_timer_read()
71 return ptimer_get_count(s->timer); in sh_timer_read()
[all …]
/openbmc/u-boot/lib/bzip2/
H A Dbzlib_decompress.c5 /*-------------------------------------------------------------*/
6 /*--- Decompression machinery ---*/
7 /*--- decompress.c ---*/
8 /*-------------------------------------------------------------*/
10 /*--
12 library for lossless, block-sorting data compression.
14 Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
62 --*/
68 /*---------------------------------------------------*/
70 void makeMaps_d ( DState* s ) in makeMaps_d() argument
[all …]
/openbmc/qemu/hw/misc/
H A Dibm-cffps.c7 * COPYING file in the top-level directory.
41 #define TYPE_IBM_CFFPS "ibm-cffps"
44 static void ibm_cffps_read(IBMCffpsState *s) in ibm_cffps_read() argument
46 s->len = 0; in ibm_cffps_read()
48 switch (s->pointer) { in ibm_cffps_read()
50 s->buf[s->len++] = 7; /* Byte count */ in ibm_cffps_read()
51 s->buf[s->len++] = 'F'; in ibm_cffps_read()
52 s->buf[s->len++] = 'R'; in ibm_cffps_read()
53 s->buf[s->len++] = 'U'; in ibm_cffps_read()
54 s->buf[s->len++] = '0'; in ibm_cffps_read()
[all …]
H A Dmos6522.c4 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Copyright (c) 2018 Mark Cave-Ayland
30 #include "hw/qdev-properties.h"
34 #include "qapi/type-helpers.h"
49 static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti,
51 static void mos6522_timer2_update(MOS6522State *s, MOS6522Timer *ti,
54 static void mos6522_update_irq(MOS6522State *s) in mos6522_update_irq() argument
56 if (s->ifr & s->ier) { in mos6522_update_irq()
57 qemu_irq_raise(s->irq); in mos6522_update_irq()
59 qemu_irq_lower(s->irq); in mos6522_update_irq()
[all …]
H A Dimx8mp_analog.c8 * SPDX-License-Identifier: GPL-2.0-or-later
21 IMX8MPAnalogState *s = IMX8MP_ANALOG(dev); in imx8mp_analog_reset() local
23 memset(s->analog, 0, sizeof(s->analog)); in imx8mp_analog_reset()
25 s->analog[ANALOG_AUDIO_PLL1_GEN_CTRL] = 0x00002010; in imx8mp_analog_reset()
26 s->analog[ANALOG_AUDIO_PLL1_FDIV_CTL0] = 0x00145032; in imx8mp_analog_reset()
27 s->analog[ANALOG_AUDIO_PLL1_FDIV_CTL1] = 0x00000000; in imx8mp_analog_reset()
28 s->analog[ANALOG_AUDIO_PLL1_SSCG_CTRL] = 0x00000000; in imx8mp_analog_reset()
29 s->analog[ANALOG_AUDIO_PLL1_MNIT_CTRL] = 0x00100103; in imx8mp_analog_reset()
30 s->analog[ANALOG_AUDIO_PLL2_GEN_CTRL] = 0x00002010; in imx8mp_analog_reset()
31 s->analog[ANALOG_AUDIO_PLL2_FDIV_CTL0] = 0x00145032; in imx8mp_analog_reset()
[all …]
/openbmc/qemu/hw/net/can/
H A Dctucan_core.c51 frame->can_id = 0; in ctucan_buff2frame()
52 frame->can_dlc = 0; in ctucan_buff2frame()
53 frame->flags = 0; in ctucan_buff2frame()
66 frame->can_dlc = can_dlc2len(frame_form_w.s.dlc); in ctucan_buff2frame()
71 ide = frame_form_w.s.ide; in ctucan_buff2frame()
73 frame->can_id = (identifier_w.s.identifier_base << 18) | in ctucan_buff2frame()
74 identifier_w.s.identifier_ext; in ctucan_buff2frame()
75 frame->can_id |= QEMU_CAN_EFF_FLAG; in ctucan_buff2frame()
77 frame->can_id = identifier_w.s.identifier_base; in ctucan_buff2frame()
80 if (frame_form_w.s.esi_rsv) { in ctucan_buff2frame()
[all …]
/openbmc/qemu/hw/display/
H A Dati_2d.c27 static int ati_bpp_from_datatype(ATIVGAState *s) in ati_bpp_from_datatype() argument
29 switch (s->regs.dp_datatype & 0xf) { in ati_bpp_from_datatype()
41 s->regs.dp_datatype & 0xf); in ati_bpp_from_datatype()
46 #define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
48 void ati_2d_blt(ATIVGAState *s) in ati_2d_blt() argument
52 DisplaySurface *ds = qemu_console_surface(s->vga.con); in ati_2d_blt()
53 DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, in ati_2d_blt()
54 s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), in ati_2d_blt()
56 (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); in ati_2d_blt()
57 unsigned dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? in ati_2d_blt()
[all …]
H A Dati.c13 * Currently it's little more than a frame buffer with minimal functions,
22 #include "vga-access.h"
23 #include "hw/qdev-properties.h"
28 #include "qemu/error-report.h"
31 #include "hw/display/i2c-ddc.h"
52 static void ati_vga_switch_mode(ATIVGAState *s) in ati_vga_switch_mode() argument
54 DPRINTF("%d -> %d\n", in ati_vga_switch_mode()
55 s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN)); in ati_vga_switch_mode()
56 if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) { in ati_vga_switch_mode()
58 s->mode = EXT_MODE; in ati_vga_switch_mode()
[all …]

12345678910>>...48