Lines Matching +full:- +full:s
2 * RISC-V translation routines for the vector crypto extension.
25 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
27 if (CHECK(s, a)) { \
28 return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
29 gen_helper_##NAME, s); \
34 static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a)
36 return opivv_check(s, a) &&
37 s->cfg_ptr->ext_zvbc == true &&
38 s->sew == MO_64;
45 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
47 if (CHECK(s, a)) { \
48 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
49 gen_helper_##NAME, s); \
54 static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
56 return opivx_check(s, a) &&
57 s->cfg_ptr->ext_zvbc == true &&
58 s->sew == MO_64;
69 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
71 if (CHECK(s, a)) { \
78 return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \
85 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
87 if (CHECK(s, a)) { \
94 return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
100 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
102 if (CHECK(s, a)) { \
109 return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \
110 fns[s->sew]); \
115 static bool zvkb_vv_check(DisasContext *s, arg_rmrr *a)
117 return opivv_check(s, a) &&
118 (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true);
121 static bool zvkb_vx_check(DisasContext *s, arg_rmrr *a)
123 return opivx_check(s, a) &&
124 (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true);
138 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
140 if (CHECK(s, a)) { \
147 return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
157 static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
159 if (CHECK(s, a)) { \
168 data = FIELD_DP32(data, VDATA, VM, a->vm); \
169 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
170 data = FIELD_DP32(data, VDATA, VTA, s->vta); \
171 data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
172 data = FIELD_DP32(data, VDATA, VMA, s->vma); \
173 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
174 vreg_ofs(s, a->rs2), tcg_env, \
175 s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
176 data, fns[s->sew]); \
177 finalize_rvv_inst(s); \
183 static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a)
185 return s->cfg_ptr->ext_zvbb == true &&
186 require_rvv(s) &&
187 vext_check_isa_ill(s) &&
188 vext_check_ss(s, a->rd, a->rs2, a->vm);
191 static bool zvkb_opiv_check(DisasContext *s, arg_rmr *a)
193 return (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true) &&
194 require_rvv(s) &&
195 vext_check_isa_ill(s) &&
196 vext_check_ss(s, a->rd, a->rs2, a->vm);
206 static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a)
208 return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a);
211 static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a)
213 return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a);
218 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
220 if (CHECK(s, a)) { \
226 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, \
243 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
245 if (CHECK(s, a)) { \
250 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
252 decode_save_opc(s, 0); \
257 data = FIELD_DP32(data, VDATA, VM, a->vm); \
258 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
259 data = FIELD_DP32(data, VDATA, VTA, s->vta); \
260 data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
261 data = FIELD_DP32(data, VDATA, VMA, s->vma); \
265 simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data)); \
266 tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
267 tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
269 finalize_rvv_inst(s); \
275 static bool vaes_check_vv(DisasContext *s, arg_rmr *a)
277 int egw_bytes = ZVKNED_EGS << s->sew;
278 return s->cfg_ptr->ext_zvkned == true &&
279 require_rvv(s) &&
280 vext_check_isa_ill(s) &&
281 MAXSZ(s) >= egw_bytes &&
282 require_align(a->rd, s->lmul) &&
283 require_align(a->rs2, s->lmul) &&
284 s->sew == MO_32;
287 static bool vaes_check_overlap(DisasContext *s, int vd, int vs2)
289 int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul;
293 static bool vaes_check_vs(DisasContext *s, arg_rmr *a)
295 int egw_bytes = ZVKNED_EGS << s->sew;
296 return vaes_check_overlap(s, a->rd, a->rs2) &&
297 MAXSZ(s) >= egw_bytes &&
298 s->cfg_ptr->ext_zvkned == true &&
299 require_rvv(s) &&
300 vext_check_isa_ill(s) &&
301 require_align(a->rd, s->lmul) &&
302 s->sew == MO_32;
316 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
318 if (CHECK(s, a)) { \
323 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
325 decode_save_opc(s, 0); \
330 data = FIELD_DP32(data, VDATA, VM, a->vm); \
331 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
332 data = FIELD_DP32(data, VDATA, VTA, s->vta); \
333 data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
334 data = FIELD_DP32(data, VDATA, VMA, s->vma); \
338 uimm_v = tcg_constant_i32(a->rs1); \
340 simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data)); \
341 tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
342 tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
344 finalize_rvv_inst(s); \
350 static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a)
352 int egw_bytes = ZVKNED_EGS << s->sew;
353 return s->cfg_ptr->ext_zvkned == true &&
354 require_rvv(s) &&
355 vext_check_isa_ill(s) &&
356 MAXSZ(s) >= egw_bytes &&
357 s->sew == MO_32 &&
358 require_align(a->rd, s->lmul) &&
359 require_align(a->rs2, s->lmul);
362 static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a)
364 int egw_bytes = ZVKNED_EGS << s->sew;
365 return s->cfg_ptr->ext_zvkned == true &&
366 require_rvv(s) &&
367 vext_check_isa_ill(s) &&
368 MAXSZ(s) >= egw_bytes &&
369 s->sew == MO_32 &&
370 require_align(a->rd, s->lmul) &&
371 require_align(a->rs2, s->lmul);
384 static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
386 if (CHECK(s, a)) { \
390 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
392 decode_save_opc(s, 0); \
397 data = FIELD_DP32(data, VDATA, VM, a->vm); \
398 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
399 data = FIELD_DP32(data, VDATA, VTA, s->vta); \
400 data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
401 data = FIELD_DP32(data, VDATA, VMA, s->vma); \
403 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), \
404 vreg_ofs(s, a->rs2), tcg_env, \
405 s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
408 finalize_rvv_inst(s); \
414 static bool vsha_check_sew(DisasContext *s)
416 return (s->cfg_ptr->ext_zvknha == true && s->sew == MO_32) ||
417 (s->cfg_ptr->ext_zvknhb == true &&
418 (s->sew == MO_32 || s->sew == MO_64));
421 static bool vsha_check(DisasContext *s, arg_rmrr *a)
423 int egw_bytes = ZVKNH_EGS << s->sew;
424 int mult = 1 << MAX(s->lmul, 0);
425 return opivv_check(s, a) &&
426 vsha_check_sew(s) &&
427 MAXSZ(s) >= egw_bytes &&
428 !is_overlapped(a->rd, mult, a->rs1, mult) &&
429 !is_overlapped(a->rd, mult, a->rs2, mult) &&
430 s->lmul >= 0;
435 static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
437 if (vsha_check(s, a)) {
441 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
443 decode_save_opc(s, 0);
448 data = FIELD_DP32(data, VDATA, VM, a->vm);
449 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
450 data = FIELD_DP32(data, VDATA, VTA, s->vta);
451 data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
452 data = FIELD_DP32(data, VDATA, VMA, s->vma);
454 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
455 vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
456 s->cfg_ptr->vlenb, data,
457 s->sew == MO_32 ?
460 finalize_rvv_inst(s);
466 static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
468 if (vsha_check(s, a)) {
472 if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
474 decode_save_opc(s, 0);
479 data = FIELD_DP32(data, VDATA, VM, a->vm);
480 data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
481 data = FIELD_DP32(data, VDATA, VTA, s->vta);
482 data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
483 data = FIELD_DP32(data, VDATA, VMA, s->vma);
485 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
486 vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlenb,
487 s->cfg_ptr->vlenb, data,
488 s->sew == MO_32 ?
491 finalize_rvv_inst(s);
503 static inline bool vsm3_check(DisasContext *s, arg_rmrr *a)
505 int egw_bytes = ZVKSH_EGS << s->sew;
506 int mult = 1 << MAX(s->lmul, 0);
507 return s->cfg_ptr->ext_zvksh == true &&
508 require_rvv(s) &&
509 vext_check_isa_ill(s) &&
510 !is_overlapped(a->rd, mult, a->rs2, mult) &&
511 MAXSZ(s) >= egw_bytes &&
512 s->sew == MO_32;
515 static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a)
517 return vsm3_check(s, a) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
520 static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a)
522 return vsm3_check(s, a) && vext_check_ss(s, a->rd, a->rs2, a->vm);
534 static bool vgmul_check(DisasContext *s, arg_rmr *a)
536 int egw_bytes = ZVKG_EGS << s->sew;
537 return s->cfg_ptr->ext_zvkg == true &&
538 vext_check_isa_ill(s) &&
539 require_rvv(s) &&
540 MAXSZ(s) >= egw_bytes &&
541 vext_check_ss(s, a->rd, a->rs2, a->vm) &&
542 s->sew == MO_32;
547 static bool vghsh_check(DisasContext *s, arg_rmrr *a)
549 int egw_bytes = ZVKG_EGS << s->sew;
550 return s->cfg_ptr->ext_zvkg == true &&
551 opivv_check(s, a) &&
552 MAXSZ(s) >= egw_bytes &&
553 s->sew == MO_32;
564 static bool zvksed_check(DisasContext *s)
566 int egw_bytes = ZVKSED_EGS << s->sew;
567 return s->cfg_ptr->ext_zvksed == true &&
568 require_rvv(s) &&
569 vext_check_isa_ill(s) &&
570 MAXSZ(s) >= egw_bytes &&
571 s->sew == MO_32;
574 static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a)
576 return zvksed_check(s) &&
577 require_align(a->rd, s->lmul) &&
578 require_align(a->rs2, s->lmul);
583 static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a)
585 return zvksed_check(s) &&
586 require_align(a->rd, s->lmul) &&
587 require_align(a->rs2, s->lmul);
592 static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a)
594 return zvksed_check(s) &&
595 !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
596 require_align(a->rd, s->lmul);