Lines Matching +full:- +full:s
22 #include "qemu/guest-random.h"
164 #define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE) argument
165 #define NPCM7XX_SMBUS_FIFO_ENABLED(s) ((s)->fif_ctl & \ argument
168 /* VERSION fields values, read-only. */
200 static void npcm7xx_smbus_update_irq(NPCM7xxSMBusState *s) in npcm7xx_smbus_update_irq() argument
204 if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { in npcm7xx_smbus_update_irq()
205 level = !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && in npcm7xx_smbus_update_irq()
206 s->st & NPCM7XX_SMBST_NMATCH) || in npcm7xx_smbus_update_irq()
207 (s->st & NPCM7XX_SMBST_BER) || in npcm7xx_smbus_update_irq()
208 (s->st & NPCM7XX_SMBST_NEGACK) || in npcm7xx_smbus_update_irq()
209 (s->st & NPCM7XX_SMBST_SDAST) || in npcm7xx_smbus_update_irq()
210 (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && in npcm7xx_smbus_update_irq()
211 s->st & NPCM7XX_SMBST_SDAST) || in npcm7xx_smbus_update_irq()
212 (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && in npcm7xx_smbus_update_irq()
213 s->cst3 & NPCM7XX_SMBCST3_EO_BUSY) || in npcm7xx_smbus_update_irq()
214 (s->rxf_ctl & NPCM7XX_SMBRXF_CTL_THR_RXIE && in npcm7xx_smbus_update_irq()
215 s->rxf_sts & NPCM7XX_SMBRXF_STS_RX_THST) || in npcm7xx_smbus_update_irq()
216 (s->txf_ctl & NPCM7XX_SMBTXF_CTL_THR_TXIE && in npcm7xx_smbus_update_irq()
217 s->txf_sts & NPCM7XX_SMBTXF_STS_TX_THST) || in npcm7xx_smbus_update_irq()
218 (s->fif_cts & NPCM7XX_SMBFIF_CTS_RFTE_IE && in npcm7xx_smbus_update_irq()
219 s->fif_cts & NPCM7XX_SMBFIF_CTS_RXF_TXE)); in npcm7xx_smbus_update_irq()
222 s->cst2 |= NPCM7XX_SMBCST2_INTSTS; in npcm7xx_smbus_update_irq()
224 s->cst2 &= ~NPCM7XX_SMBCST2_INTSTS; in npcm7xx_smbus_update_irq()
226 qemu_set_irq(s->irq, level); in npcm7xx_smbus_update_irq()
230 static void npcm7xx_smbus_nack(NPCM7xxSMBusState *s) in npcm7xx_smbus_nack() argument
232 s->st &= ~NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_nack()
233 s->st |= NPCM7XX_SMBST_NEGACK; in npcm7xx_smbus_nack()
234 s->status = NPCM7XX_SMBUS_STATUS_NEGACK; in npcm7xx_smbus_nack()
237 static void npcm7xx_smbus_clear_buffer(NPCM7xxSMBusState *s) in npcm7xx_smbus_clear_buffer() argument
239 s->fif_cts &= ~NPCM7XX_SMBFIF_CTS_RXF_TXE; in npcm7xx_smbus_clear_buffer()
240 s->txf_sts = 0; in npcm7xx_smbus_clear_buffer()
241 s->rxf_sts = 0; in npcm7xx_smbus_clear_buffer()
244 static void npcm7xx_smbus_send_byte(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_send_byte() argument
246 int rv = i2c_send(s->bus, value); in npcm7xx_smbus_send_byte()
249 npcm7xx_smbus_nack(s); in npcm7xx_smbus_send_byte()
251 s->st |= NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_send_byte()
252 if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { in npcm7xx_smbus_send_byte()
253 s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; in npcm7xx_smbus_send_byte()
254 if (NPCM7XX_SMBTXF_STS_TX_BYTES(s->txf_sts) == in npcm7xx_smbus_send_byte()
255 NPCM7XX_SMBTXF_CTL_TX_THR(s->txf_ctl)) { in npcm7xx_smbus_send_byte()
256 s->txf_sts = NPCM7XX_SMBTXF_STS_TX_THST; in npcm7xx_smbus_send_byte()
258 s->txf_sts = 0; in npcm7xx_smbus_send_byte()
262 trace_npcm7xx_smbus_send_byte((DEVICE(s)->canonical_path), value, !rv); in npcm7xx_smbus_send_byte()
263 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_send_byte()
266 static void npcm7xx_smbus_recv_byte(NPCM7xxSMBusState *s) in npcm7xx_smbus_recv_byte() argument
268 s->sda = i2c_recv(s->bus); in npcm7xx_smbus_recv_byte()
269 s->st |= NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_recv_byte()
270 if (s->st & NPCM7XX_SMBCTL1_ACK) { in npcm7xx_smbus_recv_byte()
271 trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); in npcm7xx_smbus_recv_byte()
272 i2c_nack(s->bus); in npcm7xx_smbus_recv_byte()
273 s->st &= NPCM7XX_SMBCTL1_ACK; in npcm7xx_smbus_recv_byte()
275 trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), s->sda); in npcm7xx_smbus_recv_byte()
276 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_recv_byte()
279 static void npcm7xx_smbus_recv_fifo(NPCM7xxSMBusState *s) in npcm7xx_smbus_recv_fifo() argument
281 uint8_t expected_bytes = NPCM7XX_SMBRXF_CTL_RX_THR(s->rxf_ctl); in npcm7xx_smbus_recv_fifo()
282 uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); in npcm7xx_smbus_recv_fifo()
291 pos = (s->rx_cur + received_bytes) % NPCM7XX_SMBUS_FIFO_SIZE; in npcm7xx_smbus_recv_fifo()
292 s->rx_fifo[pos] = i2c_recv(s->bus); in npcm7xx_smbus_recv_fifo()
293 trace_npcm7xx_smbus_recv_byte((DEVICE(s)->canonical_path), in npcm7xx_smbus_recv_fifo()
294 s->rx_fifo[pos]); in npcm7xx_smbus_recv_fifo()
298 trace_npcm7xx_smbus_recv_fifo((DEVICE(s)->canonical_path), in npcm7xx_smbus_recv_fifo()
300 s->rxf_sts = received_bytes; in npcm7xx_smbus_recv_fifo()
303 "%s: invalid rx_thr value: 0x%02x\n", in npcm7xx_smbus_recv_fifo()
304 DEVICE(s)->canonical_path, expected_bytes); in npcm7xx_smbus_recv_fifo()
308 s->rxf_sts |= NPCM7XX_SMBRXF_STS_RX_THST; in npcm7xx_smbus_recv_fifo()
309 if (s->rxf_ctl & NPCM7XX_SMBRXF_CTL_LAST) { in npcm7xx_smbus_recv_fifo()
310 trace_npcm7xx_smbus_nack(DEVICE(s)->canonical_path); in npcm7xx_smbus_recv_fifo()
311 i2c_nack(s->bus); in npcm7xx_smbus_recv_fifo()
312 s->rxf_ctl &= ~NPCM7XX_SMBRXF_CTL_LAST; in npcm7xx_smbus_recv_fifo()
315 s->st |= NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_recv_fifo()
316 s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; in npcm7xx_smbus_recv_fifo()
317 } else if (!(s->rxf_ctl & NPCM7XX_SMBRXF_CTL_THR_RXIE)) { in npcm7xx_smbus_recv_fifo()
318 s->st |= NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_recv_fifo()
320 s->st &= ~NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_recv_fifo()
322 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_recv_fifo()
325 static void npcm7xx_smbus_read_byte_fifo(NPCM7xxSMBusState *s) in npcm7xx_smbus_read_byte_fifo() argument
327 uint8_t received_bytes = NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts); in npcm7xx_smbus_read_byte_fifo()
330 npcm7xx_smbus_recv_fifo(s); in npcm7xx_smbus_read_byte_fifo()
334 s->sda = s->rx_fifo[s->rx_cur]; in npcm7xx_smbus_read_byte_fifo()
335 s->rx_cur = (s->rx_cur + 1u) % NPCM7XX_SMBUS_FIFO_SIZE; in npcm7xx_smbus_read_byte_fifo()
336 --s->rxf_sts; in npcm7xx_smbus_read_byte_fifo()
337 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_read_byte_fifo()
340 static void npcm7xx_smbus_start(NPCM7xxSMBusState *s) in npcm7xx_smbus_start() argument
345 * 2. We are the occupier (it's a repeated start condition.) in npcm7xx_smbus_start()
347 int available = !i2c_bus_busy(s->bus) || in npcm7xx_smbus_start()
348 s->status != NPCM7XX_SMBUS_STATUS_IDLE; in npcm7xx_smbus_start()
351 s->st |= NPCM7XX_SMBST_MODE | NPCM7XX_SMBST_XMIT | NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_start()
352 s->cst |= NPCM7XX_SMBCST_BUSY; in npcm7xx_smbus_start()
353 if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { in npcm7xx_smbus_start()
354 s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; in npcm7xx_smbus_start()
357 s->st &= ~NPCM7XX_SMBST_MODE; in npcm7xx_smbus_start()
358 s->cst &= ~NPCM7XX_SMBCST_BUSY; in npcm7xx_smbus_start()
359 s->st |= NPCM7XX_SMBST_BER; in npcm7xx_smbus_start()
362 trace_npcm7xx_smbus_start(DEVICE(s)->canonical_path, available); in npcm7xx_smbus_start()
363 s->cst |= NPCM7XX_SMBCST_BB; in npcm7xx_smbus_start()
364 s->status = NPCM7XX_SMBUS_STATUS_IDLE; in npcm7xx_smbus_start()
365 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_start()
368 static void npcm7xx_smbus_send_address(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_send_address() argument
374 rv = i2c_start_transfer(s->bus, value >> 1, recv); in npcm7xx_smbus_send_address()
375 trace_npcm7xx_smbus_send_address(DEVICE(s)->canonical_path, in npcm7xx_smbus_send_address()
379 "%s: requesting i2c bus for 0x%02x failed: %d\n", in npcm7xx_smbus_send_address()
380 DEVICE(s)->canonical_path, value, rv); in npcm7xx_smbus_send_address()
383 s->st &= ~NPCM7XX_SMBST_XMIT; in npcm7xx_smbus_send_address()
385 s->st |= NPCM7XX_SMBST_XMIT; in npcm7xx_smbus_send_address()
387 npcm7xx_smbus_nack(s); in npcm7xx_smbus_send_address()
388 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_send_address()
392 s->st &= ~NPCM7XX_SMBST_NEGACK; in npcm7xx_smbus_send_address()
394 s->status = NPCM7XX_SMBUS_STATUS_RECEIVING; in npcm7xx_smbus_send_address()
395 s->st &= ~NPCM7XX_SMBST_XMIT; in npcm7xx_smbus_send_address()
397 s->status = NPCM7XX_SMBUS_STATUS_SENDING; in npcm7xx_smbus_send_address()
398 s->st |= NPCM7XX_SMBST_XMIT; in npcm7xx_smbus_send_address()
401 if (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE) { in npcm7xx_smbus_send_address()
402 s->st |= NPCM7XX_SMBST_STASTR; in npcm7xx_smbus_send_address()
404 s->st |= NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_send_address()
407 s->st |= NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_send_address()
408 if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { in npcm7xx_smbus_send_address()
409 npcm7xx_smbus_recv_fifo(s); in npcm7xx_smbus_send_address()
411 npcm7xx_smbus_recv_byte(s); in npcm7xx_smbus_send_address()
413 } else if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { in npcm7xx_smbus_send_address()
414 s->st |= NPCM7XX_SMBST_SDAST; in npcm7xx_smbus_send_address()
415 s->fif_cts |= NPCM7XX_SMBFIF_CTS_RXF_TXE; in npcm7xx_smbus_send_address()
417 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_send_address()
420 static void npcm7xx_smbus_execute_stop(NPCM7xxSMBusState *s) in npcm7xx_smbus_execute_stop() argument
422 i2c_end_transfer(s->bus); in npcm7xx_smbus_execute_stop()
423 s->st = 0; in npcm7xx_smbus_execute_stop()
424 s->cst = 0; in npcm7xx_smbus_execute_stop()
425 s->status = NPCM7XX_SMBUS_STATUS_IDLE; in npcm7xx_smbus_execute_stop()
426 s->cst3 |= NPCM7XX_SMBCST3_EO_BUSY; in npcm7xx_smbus_execute_stop()
427 trace_npcm7xx_smbus_stop(DEVICE(s)->canonical_path); in npcm7xx_smbus_execute_stop()
428 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_execute_stop()
432 static void npcm7xx_smbus_stop(NPCM7xxSMBusState *s) in npcm7xx_smbus_stop() argument
434 if (s->st & NPCM7XX_SMBST_MODE) { in npcm7xx_smbus_stop()
435 switch (s->status) { in npcm7xx_smbus_stop()
438 s->status = NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE; in npcm7xx_smbus_stop()
442 s->status = NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK; in npcm7xx_smbus_stop()
446 npcm7xx_smbus_execute_stop(s); in npcm7xx_smbus_stop()
452 static uint8_t npcm7xx_smbus_read_sda(NPCM7xxSMBusState *s) in npcm7xx_smbus_read_sda() argument
454 uint8_t value = s->sda; in npcm7xx_smbus_read_sda()
456 switch (s->status) { in npcm7xx_smbus_read_sda()
458 if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { in npcm7xx_smbus_read_sda()
459 if (NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) <= 1) { in npcm7xx_smbus_read_sda()
460 npcm7xx_smbus_execute_stop(s); in npcm7xx_smbus_read_sda()
462 if (NPCM7XX_SMBRXF_STS_RX_BYTES(s->rxf_sts) == 0) { in npcm7xx_smbus_read_sda()
464 "%s: read to SDA with an empty rx-fifo buffer, " in npcm7xx_smbus_read_sda()
466 DEVICE(s)->canonical_path, s->sda); in npcm7xx_smbus_read_sda()
469 npcm7xx_smbus_read_byte_fifo(s); in npcm7xx_smbus_read_sda()
470 value = s->sda; in npcm7xx_smbus_read_sda()
472 npcm7xx_smbus_execute_stop(s); in npcm7xx_smbus_read_sda()
477 if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { in npcm7xx_smbus_read_sda()
478 npcm7xx_smbus_read_byte_fifo(s); in npcm7xx_smbus_read_sda()
479 value = s->sda; in npcm7xx_smbus_read_sda()
481 npcm7xx_smbus_recv_byte(s); in npcm7xx_smbus_read_sda()
493 static void npcm7xx_smbus_write_sda(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_sda() argument
495 s->sda = value; in npcm7xx_smbus_write_sda()
496 if (s->st & NPCM7XX_SMBST_MODE) { in npcm7xx_smbus_write_sda()
497 switch (s->status) { in npcm7xx_smbus_write_sda()
499 npcm7xx_smbus_send_address(s, value); in npcm7xx_smbus_write_sda()
502 npcm7xx_smbus_send_byte(s, value); in npcm7xx_smbus_write_sda()
506 "%s: write to SDA in invalid status %d: %u\n", in npcm7xx_smbus_write_sda()
507 DEVICE(s)->canonical_path, s->status, value); in npcm7xx_smbus_write_sda()
513 static void npcm7xx_smbus_write_st(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_st() argument
515 s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STP); in npcm7xx_smbus_write_st()
516 s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_BER); in npcm7xx_smbus_write_st()
517 s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_STASTR); in npcm7xx_smbus_write_st()
518 s->st = WRITE_ONE_CLEAR(s->st, value, NPCM7XX_SMBST_NMATCH); in npcm7xx_smbus_write_st()
521 s->st &= ~NPCM7XX_SMBST_NEGACK; in npcm7xx_smbus_write_st()
522 if (s->status == NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK) { in npcm7xx_smbus_write_st()
523 npcm7xx_smbus_execute_stop(s); in npcm7xx_smbus_write_st()
528 s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { in npcm7xx_smbus_write_st()
529 if (NPCM7XX_SMBUS_FIFO_ENABLED(s)) { in npcm7xx_smbus_write_st()
530 npcm7xx_smbus_recv_fifo(s); in npcm7xx_smbus_write_st()
532 npcm7xx_smbus_recv_byte(s); in npcm7xx_smbus_write_st()
536 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_write_st()
539 static void npcm7xx_smbus_write_cst(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_cst() argument
541 uint8_t new_value = s->cst; in npcm7xx_smbus_write_cst()
543 s->cst = WRITE_ONE_CLEAR(new_value, value, NPCM7XX_SMBCST_BB); in npcm7xx_smbus_write_cst()
544 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_write_cst()
547 static void npcm7xx_smbus_write_cst3(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_cst3() argument
549 s->cst3 = WRITE_ONE_CLEAR(s->cst3, value, NPCM7XX_SMBCST3_EO_BUSY); in npcm7xx_smbus_write_cst3()
550 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_write_cst3()
553 static void npcm7xx_smbus_write_ctl1(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_ctl1() argument
555 s->ctl1 = KEEP_OLD_BIT(s->ctl1, value, in npcm7xx_smbus_write_ctl1()
559 npcm7xx_smbus_start(s); in npcm7xx_smbus_write_ctl1()
563 npcm7xx_smbus_stop(s); in npcm7xx_smbus_write_ctl1()
566 npcm7xx_smbus_update_irq(s); in npcm7xx_smbus_write_ctl1()
569 static void npcm7xx_smbus_write_ctl2(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_ctl2() argument
571 s->ctl2 = value; in npcm7xx_smbus_write_ctl2()
573 if (!NPCM7XX_SMBUS_ENABLED(s)) { in npcm7xx_smbus_write_ctl2()
575 s->ctl1 = 0; in npcm7xx_smbus_write_ctl2()
576 s->st = 0; in npcm7xx_smbus_write_ctl2()
577 s->cst3 = s->cst3 & (~NPCM7XX_SMBCST3_EO_BUSY); in npcm7xx_smbus_write_ctl2()
578 s->cst = 0; in npcm7xx_smbus_write_ctl2()
579 npcm7xx_smbus_clear_buffer(s); in npcm7xx_smbus_write_ctl2()
583 static void npcm7xx_smbus_write_ctl3(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_ctl3() argument
585 uint8_t old_ctl3 = s->ctl3; in npcm7xx_smbus_write_ctl3()
588 s->ctl3 = KEEP_OLD_BIT(old_ctl3, value, in npcm7xx_smbus_write_ctl3()
592 static void npcm7xx_smbus_write_fif_ctl(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_fif_ctl() argument
596 new_ctl = KEEP_OLD_BIT(s->fif_ctl, new_ctl, NPCM7XX_SMBFIF_CTL_FAIR_RDY); in npcm7xx_smbus_write_fif_ctl()
598 new_ctl = KEEP_OLD_BIT(s->fif_ctl, new_ctl, NPCM7XX_SMBFIF_CTL_FAIR_BUSY); in npcm7xx_smbus_write_fif_ctl()
599 s->fif_ctl = new_ctl; in npcm7xx_smbus_write_fif_ctl()
602 static void npcm7xx_smbus_write_fif_cts(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_fif_cts() argument
604 s->fif_cts = WRITE_ONE_CLEAR(s->fif_cts, value, NPCM7XX_SMBFIF_CTS_STR); in npcm7xx_smbus_write_fif_cts()
605 s->fif_cts = WRITE_ONE_CLEAR(s->fif_cts, value, NPCM7XX_SMBFIF_CTS_RXF_TXE); in npcm7xx_smbus_write_fif_cts()
606 s->fif_cts = KEEP_OLD_BIT(value, s->fif_cts, NPCM7XX_SMBFIF_CTS_RFTE_IE); in npcm7xx_smbus_write_fif_cts()
609 npcm7xx_smbus_clear_buffer(s); in npcm7xx_smbus_write_fif_cts()
613 static void npcm7xx_smbus_write_txf_ctl(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_txf_ctl() argument
615 s->txf_ctl = value; in npcm7xx_smbus_write_txf_ctl()
618 static void npcm7xx_smbus_write_t_out(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_t_out() argument
622 if ((value & NPCM7XX_SMBT_OUT_ST) || (!(s->t_out & NPCM7XX_SMBT_OUT_ST))) { in npcm7xx_smbus_write_t_out()
628 s->t_out = new_t_out; in npcm7xx_smbus_write_t_out()
631 static void npcm7xx_smbus_write_txf_sts(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_txf_sts() argument
633 s->txf_sts = WRITE_ONE_CLEAR(s->txf_sts, value, NPCM7XX_SMBTXF_STS_TX_THST); in npcm7xx_smbus_write_txf_sts()
636 static void npcm7xx_smbus_write_rxf_sts(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_rxf_sts() argument
639 s->rxf_sts &= ~NPCM7XX_SMBRXF_STS_RX_THST; in npcm7xx_smbus_write_rxf_sts()
640 if (s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { in npcm7xx_smbus_write_rxf_sts()
641 npcm7xx_smbus_recv_fifo(s); in npcm7xx_smbus_write_rxf_sts()
646 static void npcm7xx_smbus_write_rxf_ctl(NPCM7xxSMBusState *s, uint8_t value) in npcm7xx_smbus_write_rxf_ctl() argument
651 new_ctl = KEEP_OLD_BIT(s->rxf_ctl, new_ctl, NPCM7XX_SMBRXF_CTL_LAST); in npcm7xx_smbus_write_rxf_ctl()
653 s->rxf_ctl = new_ctl; in npcm7xx_smbus_write_rxf_ctl()
658 NPCM7xxSMBusState *s = opaque; in npcm7xx_smbus_read() local
660 uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; in npcm7xx_smbus_read()
665 value = npcm7xx_smbus_read_sda(s); in npcm7xx_smbus_read()
669 value = s->st; in npcm7xx_smbus_read()
673 value = s->cst; in npcm7xx_smbus_read()
677 value = s->ctl1; in npcm7xx_smbus_read()
681 value = s->addr[0]; in npcm7xx_smbus_read()
685 value = s->ctl2; in npcm7xx_smbus_read()
689 value = s->addr[1]; in npcm7xx_smbus_read()
693 value = s->ctl3; in npcm7xx_smbus_read()
697 value = s->cst2; in npcm7xx_smbus_read()
701 value = s->cst3; in npcm7xx_smbus_read()
714 value = s->fif_cts; in npcm7xx_smbus_read()
718 value = s->fair_per; in npcm7xx_smbus_read()
722 value = s->txf_ctl; in npcm7xx_smbus_read()
726 value = s->t_out; in npcm7xx_smbus_read()
730 value = s->txf_sts; in npcm7xx_smbus_read()
734 value = s->rxf_sts; in npcm7xx_smbus_read()
738 value = s->rxf_ctl; in npcm7xx_smbus_read()
743 "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_read()
744 DEVICE(s)->canonical_path, offset); in npcm7xx_smbus_read()
751 value = s->addr[2]; in npcm7xx_smbus_read()
755 value = s->addr[6]; in npcm7xx_smbus_read()
759 value = s->addr[3]; in npcm7xx_smbus_read()
763 value = s->addr[7]; in npcm7xx_smbus_read()
767 value = s->addr[4]; in npcm7xx_smbus_read()
771 value = s->addr[8]; in npcm7xx_smbus_read()
775 value = s->addr[5]; in npcm7xx_smbus_read()
779 value = s->addr[9]; in npcm7xx_smbus_read()
783 value = s->ctl4; in npcm7xx_smbus_read()
787 value = s->ctl5; in npcm7xx_smbus_read()
791 value = s->scllt; in npcm7xx_smbus_read()
795 value = s->fif_ctl; in npcm7xx_smbus_read()
799 value = s->sclht; in npcm7xx_smbus_read()
804 "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_read()
805 DEVICE(s)->canonical_path, offset); in npcm7xx_smbus_read()
812 trace_npcm7xx_smbus_read(DEVICE(s)->canonical_path, offset, value, size); in npcm7xx_smbus_read()
820 NPCM7xxSMBusState *s = opaque; in npcm7xx_smbus_write() local
821 uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; in npcm7xx_smbus_write()
823 trace_npcm7xx_smbus_write(DEVICE(s)->canonical_path, offset, value, size); in npcm7xx_smbus_write()
828 npcm7xx_smbus_write_sda(s, value); in npcm7xx_smbus_write()
832 npcm7xx_smbus_write_st(s, value); in npcm7xx_smbus_write()
836 npcm7xx_smbus_write_cst(s, value); in npcm7xx_smbus_write()
840 npcm7xx_smbus_write_ctl1(s, value); in npcm7xx_smbus_write()
844 s->addr[0] = value; in npcm7xx_smbus_write()
848 npcm7xx_smbus_write_ctl2(s, value); in npcm7xx_smbus_write()
852 s->addr[1] = value; in npcm7xx_smbus_write()
856 npcm7xx_smbus_write_ctl3(s, value); in npcm7xx_smbus_write()
861 "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_write()
862 DEVICE(s)->canonical_path, offset); in npcm7xx_smbus_write()
866 npcm7xx_smbus_write_cst3(s, value); in npcm7xx_smbus_write()
871 "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_write()
872 DEVICE(s)->canonical_path, offset); in npcm7xx_smbus_write()
881 npcm7xx_smbus_write_fif_cts(s, value); in npcm7xx_smbus_write()
885 s->fair_per = value; in npcm7xx_smbus_write()
889 npcm7xx_smbus_write_txf_ctl(s, value); in npcm7xx_smbus_write()
893 npcm7xx_smbus_write_t_out(s, value); in npcm7xx_smbus_write()
897 npcm7xx_smbus_write_txf_sts(s, value); in npcm7xx_smbus_write()
901 npcm7xx_smbus_write_rxf_sts(s, value); in npcm7xx_smbus_write()
905 npcm7xx_smbus_write_rxf_ctl(s, value); in npcm7xx_smbus_write()
910 "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_write()
911 DEVICE(s)->canonical_path, offset); in npcm7xx_smbus_write()
918 s->addr[2] = value; in npcm7xx_smbus_write()
922 s->addr[6] = value; in npcm7xx_smbus_write()
926 s->addr[3] = value; in npcm7xx_smbus_write()
930 s->addr[7] = value; in npcm7xx_smbus_write()
934 s->addr[4] = value; in npcm7xx_smbus_write()
938 s->addr[8] = value; in npcm7xx_smbus_write()
942 s->addr[5] = value; in npcm7xx_smbus_write()
946 s->addr[9] = value; in npcm7xx_smbus_write()
950 s->ctl4 = value; in npcm7xx_smbus_write()
954 s->ctl5 = value; in npcm7xx_smbus_write()
958 s->scllt = value; in npcm7xx_smbus_write()
962 npcm7xx_smbus_write_fif_ctl(s, value); in npcm7xx_smbus_write()
966 s->sclht = value; in npcm7xx_smbus_write()
971 "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_write()
972 DEVICE(s)->canonical_path, offset); in npcm7xx_smbus_write()
993 NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); in npcm7xx_smbus_enter_reset() local
995 s->st = NPCM7XX_SMB_ST_INIT_VAL; in npcm7xx_smbus_enter_reset()
996 s->cst = NPCM7XX_SMB_CST_INIT_VAL; in npcm7xx_smbus_enter_reset()
997 s->cst2 = NPCM7XX_SMB_CST2_INIT_VAL; in npcm7xx_smbus_enter_reset()
998 s->cst3 = NPCM7XX_SMB_CST3_INIT_VAL; in npcm7xx_smbus_enter_reset()
999 s->ctl1 = NPCM7XX_SMB_CTL1_INIT_VAL; in npcm7xx_smbus_enter_reset()
1000 s->ctl2 = NPCM7XX_SMB_CTL2_INIT_VAL; in npcm7xx_smbus_enter_reset()
1001 s->ctl3 = NPCM7XX_SMB_CTL3_INIT_VAL; in npcm7xx_smbus_enter_reset()
1002 s->ctl4 = NPCM7XX_SMB_CTL4_INIT_VAL; in npcm7xx_smbus_enter_reset()
1003 s->ctl5 = NPCM7XX_SMB_CTL5_INIT_VAL; in npcm7xx_smbus_enter_reset()
1006 s->addr[i] = NPCM7XX_SMB_ADDR_INIT_VAL; in npcm7xx_smbus_enter_reset()
1008 s->scllt = NPCM7XX_SMB_SCLLT_INIT_VAL; in npcm7xx_smbus_enter_reset()
1009 s->sclht = NPCM7XX_SMB_SCLHT_INIT_VAL; in npcm7xx_smbus_enter_reset()
1011 s->fif_ctl = NPCM7XX_SMB_FIF_CTL_INIT_VAL; in npcm7xx_smbus_enter_reset()
1012 s->fif_cts = NPCM7XX_SMB_FIF_CTS_INIT_VAL; in npcm7xx_smbus_enter_reset()
1013 s->fair_per = NPCM7XX_SMB_FAIR_PER_INIT_VAL; in npcm7xx_smbus_enter_reset()
1014 s->txf_ctl = NPCM7XX_SMB_TXF_CTL_INIT_VAL; in npcm7xx_smbus_enter_reset()
1015 s->t_out = NPCM7XX_SMB_T_OUT_INIT_VAL; in npcm7xx_smbus_enter_reset()
1016 s->txf_sts = NPCM7XX_SMB_TXF_STS_INIT_VAL; in npcm7xx_smbus_enter_reset()
1017 s->rxf_sts = NPCM7XX_SMB_RXF_STS_INIT_VAL; in npcm7xx_smbus_enter_reset()
1018 s->rxf_ctl = NPCM7XX_SMB_RXF_CTL_INIT_VAL; in npcm7xx_smbus_enter_reset()
1020 npcm7xx_smbus_clear_buffer(s); in npcm7xx_smbus_enter_reset()
1021 s->status = NPCM7XX_SMBUS_STATUS_IDLE; in npcm7xx_smbus_enter_reset()
1022 s->rx_cur = 0; in npcm7xx_smbus_enter_reset()
1027 NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); in npcm7xx_smbus_hold_reset() local
1029 qemu_irq_lower(s->irq); in npcm7xx_smbus_hold_reset()
1034 NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj); in npcm7xx_smbus_init() local
1037 sysbus_init_irq(sbd, &s->irq); in npcm7xx_smbus_init()
1038 memory_region_init_io(&s->iomem, obj, &npcm7xx_smbus_ops, s, in npcm7xx_smbus_init()
1040 sysbus_init_mmio(sbd, &s->iomem); in npcm7xx_smbus_init()
1042 s->bus = i2c_init_bus(DEVICE(s), "i2c-bus"); in npcm7xx_smbus_init()
1046 .name = "npcm7xx-smbus",
1083 dc->desc = "NPCM7xx System Management Bus"; in npcm7xx_smbus_class_init()
1084 dc->vmsd = &vmstate_npcm7xx_smbus; in npcm7xx_smbus_class_init()
1085 rc->phases.enter = npcm7xx_smbus_enter_reset; in npcm7xx_smbus_class_init()
1086 rc->phases.hold = npcm7xx_smbus_hold_reset; in npcm7xx_smbus_class_init()