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/openbmc/openbmc/meta-quanta/meta-gbs/recipes-phosphor/sensors/phosphor-hwmon/obmc/hwmon/ahb/apb/i2c@88000/
H A Dadm1272@10.conf2 CRITHI_in1 = "60000"
4 WARNHI_in1 = "60000"
10 CRITHI_in2 = "60000"
12 WARNHI_in2 = "60000"
18 CRITHI_curr1= "60000"
20 WARNHI_curr1= "60000"
42 MINVALUE_temp1 = "-128"
/openbmc/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
18 * of the D-PHY specification (v1.2).
29 return -EINVAL; in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
42 cfg->clk_prepare = 38000; in phy_mipi_dphy_calc_config()
43 cfg->clk_settle = 95000; in phy_mipi_dphy_calc_config()
[all …]
/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Dconnect_force_port4.c1 // SPDX-License-Identifier: GPL-2.0
43 /* Rewire service 1.2.3.4:60000 to backend 127.0.0.1:60123. */ in connect4()
44 if (ctx->user_port == bpf_htons(60000)) { in connect4()
45 orig = bpf_sk_storage_get(&service_mapping, ctx->sk, 0, in connect4()
50 orig->addr = ctx->user_ip4; in connect4()
51 orig->port = ctx->user_port; in connect4()
53 ctx->user_ip4 = bpf_htonl(0x7f000001); in connect4()
54 ctx->user_port = bpf_htons(60123); in connect4()
65 /* Expose local server as 1.2.3.4:60000 to client. */ in getsockname4()
66 if (ctx->user_port == bpf_htons(60123)) { in getsockname4()
[all …]
H A Dconnect_force_port6.c1 // SPDX-License-Identifier: GPL-2.0
42 /* Rewire service [fc00::1]:60000 to backend [::1]:60124. */ in connect6()
43 if (ctx->user_port == bpf_htons(60000)) { in connect6()
44 orig = bpf_sk_storage_get(&service_mapping, ctx->sk, 0, in connect6()
49 orig->addr[0] = ctx->user_ip6[0]; in connect6()
50 orig->addr[1] = ctx->user_ip6[1]; in connect6()
51 orig->addr[2] = ctx->user_ip6[2]; in connect6()
52 orig->addr[3] = ctx->user_ip6[3]; in connect6()
53 orig->port = ctx->user_port; in connect6()
55 ctx->user_ip6[0] = 0; in connect6()
[all …]
/openbmc/u-boot/board/Marvell/db-88f6820-gp/
H A DREADME1 Update from original Marvell U-Boot to mainline U-Boot:
2 -------------------------------------------------------
5 full DDR setup is "u-boot-spl.kwb".
10 => sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\
11 sf update 2000000 0 60000
13 Note that the original Marvell U-Boot seems to have
17 => sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\
18 sf erase 0 60000;sf write 2000000 0 60000
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-crs328-4c-20s-4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS328-4C-20S-4S+ board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS328-4C-20S-4S+";
25 compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
38 arm,parity-enable;
39 marvell,ecc-enable;
[all …]
H A Darmada-xp-crs305-1g-4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS305-1G-4S board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS305-1G-4S+";
25 compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
38 arm,parity-enable;
39 marvell,ecc-enable;
[all …]
H A Darmada-xp-crs326-24g-2s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CRS326-24G-2S board
8 * Based on armada-xp-db.dts
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
20 /dts-v1/;
21 #include "armada-xp-98dx3236.dtsi"
24 model = "CRS326-24G-2S+";
25 compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
38 arm,parity-enable;
39 marvell,ecc-enable;
[all …]
H A Darmada-xp-db-xc3-24g4xg.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-XC3-24G4XG board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx3336.dtsi"
23 model = "DB-XC3-24G4XG";
24 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
37 arm,parity-enable;
38 marvell,ecc-enable;
[all …]
H A Darmada-xp-db-dxbc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-DXBC2 board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx4251.dtsi"
24 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
43 devbus,bus-width = <16>;
44 devbus,turn-off-ps = <60000>;
45 devbus,badr-skew-ps = <0>;
[all …]
H A Darmada-xp-openblocks-ax3-4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for OpenBlocks AX3-4 board
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "armada-xp-mv78260.dtsi"
16 model = "PlatHome OpenBlocks AX3-4 board";
17 …compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell…
20 stdout-path = "serial0:115200n8";
[all …]
H A Darmada-385-atl-x530.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 (x530/AT-GS980MX)
9 /dts-v1/;
10 #include "armada-385.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
15 model = "x530/AT-GS980MX";
19 stdout-path = "serial1:115200n8";
32 internal-regs {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins>;
[all …]
H A Darmada-xp-gp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-MV784MP-GP)
6 * Copyright (C) 2013-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include "armada-xp-mv78460.dtsi"
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
[all …]
H A Darmada-xp-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-78460-BP)
6 * Copyright (C) 2012-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
23 /dts-v1/;
24 #include "armada-xp-mv78460.dtsi"
28 …compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
31 stdout-path = "serial0:115200n8";
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor-pompom.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "sc7180-trogdor.dtsi"
9 /* Must come after sc7180-trogdor.dtsi to modify cros_ec */
10 #include <arm/cros-ec-keyboard.dtsi>
11 #include "sc7180-trogdor-ti-sn65dsi86.dtsi"
14 thermal-zones {
15 5v-choke-thermal {
16 polling-delay-passive = <0>;
17 polling-delay = <250>;
19 thermal-sensors = <&pm6150_adc_tm 1>;
[all …]
/openbmc/openbmc/meta-quanta/meta-gbs/recipes-phosphor/sensors/phosphor-hwmon/obmc/hwmon/ahb/apb/i2c@8c000/
H A Dvrm@5d.conf2 CRITHI_in1 = "60000"
4 WARNHI_in1 = "60000"
25 CRITLO_curr1 = "-1000"
27 WARNLO_curr1 = "-1000"
36 CRITLO_curr2 = "-1000"
38 WARNLO_curr2 = "-1000"
48 MINVALUE_temp1 = "-128"
H A Dvrm@5e.conf2 CRITHI_in1 = "60000"
4 WARNHI_in1 = "60000"
48 MINVALUE_temp1 = "-128"
/openbmc/u-boot/arch/arm/dts/
H A Darmada-385-atl-x530.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/gpio.h>
4 #include "armada-385.dtsi"
11 stdout-path = "serial0:115200n8";
30 pcie-mem-aperture = <0xa0000000 0x40000000>;
33 eco-button-interrupt {
34 compatible = "atl,eco-button-interrupt";
35 eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
38 board-reset {
40 /* Physical board layout of reset pin is active-low but for the
[all …]
H A Darmada-xp-maxbcm.dts4 * Copyright (C) 2013-2014 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
51 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
58 /dts-v1/;
59 #include <dt-bindings/gpio/gpio.h>
60 #include "armada-xp-mv78460.dtsi"
64 …compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
67 stdout-path = "serial0:115200n8";
[all …]
H A Darmada-xp-gp.dts3 * (DB-MV784MP-GP)
5 * Copyright (C) 2013-2014 Marvell
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is dual-licensed: you can use it either under the terms
52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
59 /dts-v1/;
60 #include <dt-bindings/gpio/gpio.h>
61 #include "armada-xp-mv78460.dtsi"
64 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
/openbmc/linux/include/linux/phy/
H A Dphy-mipi-dphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
22 * Maximum value: 60000 ps
34 * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps
53 * Lane LP-00 Line state immediately before the HS-0 Line
86 * Time, in picoseconds, that the transmitter drives the HS-0
90 * Minimum value: 60000 ps
97 * Time, in picoseconds, that the transmitter drives the HS-0
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dtout.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
17 [MLX5_TO_CMD_MS] = 60000,
20 [MLX5_TO_FULL_CRDUMP_MS] = 60000,
21 [MLX5_TO_FW_RESET_MS] = 60000,
33 dev->timeouts->to[type] = val; in tout_set()
40 dev->timeouts = kmalloc(sizeof(*dev->timeouts), GFP_KERNEL); in mlx5_tout_init()
41 if (!dev->timeouts) in mlx5_tout_init()
42 return -ENOMEM; in mlx5_tout_init()
52 kfree(dev->timeouts); in mlx5_tout_cleanup()
72 msec *= 1000 * int_pow(60, to_mul - 1); in tout_convert_reg_field_to_ms()
[all …]
/openbmc/u-boot/doc/
H A DREADME.sha12 -----------
4 In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated.
5 This SHA1 sum is used, to check, if the U-Boot Image in Flash is not
12 -p calculate the SHA1 sum from the U-Boot image in flash and print
13 -c check the U-Boot image in flash
15 "sha1 -p"
18 "sha1 -c"
33 "cp.b fffa0000 300000 60000"
38 for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20
40 for the example in RAM: 0x300000 + 0x60000 + -0x20
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-connectivity/thingsboard-gateway/thingsboard-gateway/
H A Dmqtt.json20 "timeout": 60000,
53 "timeout": 60000,
80 "extension-config": {
127 "methodFilter": "no-reply",

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