1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Device Tree file for DB-XC3-24G4XG board
4*724ba675SRob Herring *
5*724ba675SRob Herring * Copyright (C) 2016 Allied Telesis Labs
6*724ba675SRob Herring *
7*724ba675SRob Herring * Based on armada-xp-db.dts
8*724ba675SRob Herring *
9*724ba675SRob Herring * Note: this Device Tree assumes that the bootloader has remapped the
10*724ba675SRob Herring * internal registers to 0xf1000000 (instead of the default
11*724ba675SRob Herring * 0xd0000000). The 0xf1000000 is the default used by the recent,
12*724ba675SRob Herring * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
13*724ba675SRob Herring * boards were delivered with an older version of the bootloader that
14*724ba675SRob Herring * left internal registers mapped at 0xd0000000. If you are in this
15*724ba675SRob Herring * situation, you should either update your bootloader (preferred
16*724ba675SRob Herring * solution) or the below Device Tree should be adjusted.
17*724ba675SRob Herring */
18*724ba675SRob Herring
19*724ba675SRob Herring/dts-v1/;
20*724ba675SRob Herring#include "armada-xp-98dx3336.dtsi"
21*724ba675SRob Herring
22*724ba675SRob Herring/ {
23*724ba675SRob Herring	model = "DB-XC3-24G4XG";
24*724ba675SRob Herring	compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
25*724ba675SRob Herring
26*724ba675SRob Herring	chosen {
27*724ba675SRob Herring		bootargs = "console=ttyS0,115200 earlyprintk";
28*724ba675SRob Herring	};
29*724ba675SRob Herring
30*724ba675SRob Herring	memory {
31*724ba675SRob Herring		device_type = "memory";
32*724ba675SRob Herring		reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
33*724ba675SRob Herring	};
34*724ba675SRob Herring};
35*724ba675SRob Herring
36*724ba675SRob Herring&L2 {
37*724ba675SRob Herring	arm,parity-enable;
38*724ba675SRob Herring	marvell,ecc-enable;
39*724ba675SRob Herring};
40*724ba675SRob Herring
41*724ba675SRob Herring&devbus_bootcs {
42*724ba675SRob Herring	status = "okay";
43*724ba675SRob Herring
44*724ba675SRob Herring	/* Device Bus parameters are required */
45*724ba675SRob Herring
46*724ba675SRob Herring	/* Read parameters */
47*724ba675SRob Herring	devbus,bus-width    = <16>;
48*724ba675SRob Herring	devbus,turn-off-ps  = <60000>;
49*724ba675SRob Herring	devbus,badr-skew-ps = <0>;
50*724ba675SRob Herring	devbus,acc-first-ps = <124000>;
51*724ba675SRob Herring	devbus,acc-next-ps  = <248000>;
52*724ba675SRob Herring	devbus,rd-setup-ps  = <0>;
53*724ba675SRob Herring	devbus,rd-hold-ps   = <0>;
54*724ba675SRob Herring
55*724ba675SRob Herring	/* Write parameters */
56*724ba675SRob Herring	devbus,sync-enable = <0>;
57*724ba675SRob Herring	devbus,wr-high-ps  = <60000>;
58*724ba675SRob Herring	devbus,wr-low-ps   = <60000>;
59*724ba675SRob Herring	devbus,ale-wr-ps   = <60000>;
60*724ba675SRob Herring};
61*724ba675SRob Herring
62*724ba675SRob Herring&uart0 {
63*724ba675SRob Herring	status = "okay";
64*724ba675SRob Herring};
65*724ba675SRob Herring
66*724ba675SRob Herring&uart1 {
67*724ba675SRob Herring	status = "okay";
68*724ba675SRob Herring};
69*724ba675SRob Herring
70*724ba675SRob Herring&i2c0 {
71*724ba675SRob Herring	clock-frequency = <100000>;
72*724ba675SRob Herring	status = "okay";
73*724ba675SRob Herring};
74*724ba675SRob Herring
75*724ba675SRob Herring&nand_controller {
76*724ba675SRob Herring	status = "okay";
77*724ba675SRob Herring
78*724ba675SRob Herring	nand@0 {
79*724ba675SRob Herring		reg = <0>;
80*724ba675SRob Herring		label = "pxa3xx_nand-0";
81*724ba675SRob Herring		nand-rb = <0>;
82*724ba675SRob Herring		marvell,nand-keep-config;
83*724ba675SRob Herring		nand-on-flash-bbt;
84*724ba675SRob Herring		nand-ecc-strength = <4>;
85*724ba675SRob Herring		nand-ecc-step-size = <512>;
86*724ba675SRob Herring	};
87*724ba675SRob Herring};
88*724ba675SRob Herring
89*724ba675SRob Herring&spi0 {
90*724ba675SRob Herring	status = "okay";
91*724ba675SRob Herring
92*724ba675SRob Herring	flash@0 {
93*724ba675SRob Herring		#address-cells = <1>;
94*724ba675SRob Herring		#size-cells = <1>;
95*724ba675SRob Herring		compatible = "m25p64";
96*724ba675SRob Herring		reg = <0>; /* Chip select 0 */
97*724ba675SRob Herring		spi-max-frequency = <20000000>;
98*724ba675SRob Herring		m25p,fast-read;
99*724ba675SRob Herring
100*724ba675SRob Herring		partition@u-boot {
101*724ba675SRob Herring			reg = <0x00000000 0x00100000>;
102*724ba675SRob Herring			label = "u-boot";
103*724ba675SRob Herring		};
104*724ba675SRob Herring		partition@u-boot-env {
105*724ba675SRob Herring			reg = <0x00100000 0x00040000>;
106*724ba675SRob Herring			label = "u-boot-env";
107*724ba675SRob Herring		};
108*724ba675SRob Herring		partition@unused {
109*724ba675SRob Herring			reg = <0x00140000 0x00ec0000>;
110*724ba675SRob Herring			label = "unused";
111*724ba675SRob Herring		};
112*724ba675SRob Herring
113*724ba675SRob Herring	};
114*724ba675SRob Herring};
115